Patents by Inventor Hidetoshi Nishimura

Hidetoshi Nishimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050129384
    Abstract: An optical structure is disposed on a surface of a device substrate, and a lens system for introducing external light into a solid-state image pickup device is placed in the center of the optical structure. The outer shape of the optical structure seen from the light incident side of the lens system is rectangular, and its plane shape forms a rectangular frame section. An intermediate structure is disposed between the device substrate and the optical structure. The intermediate structure has a fitting section for fitting the optical structure in a part of side faces of the frame section.
    Type: Application
    Filed: December 6, 2004
    Publication date: June 16, 2005
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Katsuitsu Nishida, Tohru Shigeta, Hidetoshi Nishimura, Yoshinori Tanida
  • Patent number: 6791391
    Abstract: In a CMOS level shifting circuit including N-channel transistors that have sources to which a digital signal is supplied, a bias voltage Vref is supplied to gates of the N-channel transistors, and the bias voltage Vref is set to be higher than a high level voltage of the digital signal and lower than a value obtained by adding a threshold voltage of the N-channel transistors to the high level voltage of the digital signal. Thus, a level shifting circuit is provided that is capable of outputting a signal having subjected to stable level conversion, even when a voltage level of a low voltage signal is lowered.
    Type: Grant
    Filed: July 10, 2002
    Date of Patent: September 14, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hidetoshi Nishimura, Masahiro Gion, Heiji Ikoma, Naoki Nojiri
  • Publication number: 20030011418
    Abstract: In a CMOS level shifting circuit including N-channel transistors that have sources to which a digital signal is supplied, a bias voltage Vref is supplied to gates of the N-channel transistors, and the bias voltage Vref is set to be higher than a high level voltage of the digital signal and lower than a value obtained by adding a threshold voltage of the N-channel transistors to the high level voltage of the digital signal. Thus, a level shifting circuit is provided that is capable of outputting a signal having subjected to stable level conversion, even when a voltage level of a low voltage signal is lowered.
    Type: Application
    Filed: July 10, 2002
    Publication date: January 16, 2003
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hidetoshi Nishimura, Masahiro Gion, Heiji Ikoma, Naoki Nojiri
  • Patent number: 5761337
    Abstract: A semiconductor chip with bumps to be inspected is placed directly below a CCD, which captures an image of the bumps under dark field illumination. A reference window is set around each bump in the image. The reference window is enlarged or reduced or divided into subwindows such that optimal windows are provided for extraction of characteristic values of various defects. Characteristic values of particular defects are extracted from the image data within the corresponding optimal windows. The characteristic values for the bumps are statistically processed to obtain an evaluation value having a permissible range. The characteristic value of each bump is compared with the evaluation value and when the comparison indicates that the characteristic value is outside of the range, the bump is decided as a defective bump.
    Type: Grant
    Filed: August 5, 1996
    Date of Patent: June 2, 1998
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Hidetoshi Nishimura, Yuichi Shirouchi