Abstract: A photodetector according to one embodiment of the present disclosure includes a semiconductor layer, a plurality of pixels including a first pixel including a photoelectric conversion element provided in the semiconductor layer, and a trench provided between the plurality of pixels adjacent to each other in the semiconductor layer. The first pixel includes a transistor provided on a side of a first surface of the semiconductor layer, a first semiconductor region having a first conductivity type, which is provided on the side of the first surface of the semiconductor layer, and a first contact that is electrically coupled to the first semiconductor region. The first semiconductor region is in contact with the transistor.

Abstract: To achieve high integration and improvement in noise resistance. A semiconductor device includes first and second field-effect transistors. In addition, each of the first and second field-effect transistors includes a channel formation portion provided in a semiconductor including an upper surface and side surfaces, a gate electrode provided over the upper surface and the side surfaces in one direction of the semiconductor, and a gate insulating film provided between the semiconductor and the gate electrode. In addition, a width, in the one direction, of the upper surface of the semiconductor layer overlapping the gate electrode of the first transistor is smaller than a width, in the one direction, of the upper surface of the semiconductor layer overlapping the gate electrode of the second transistor, and a film thickness of the gate insulating film of the second transistor is smaller than a film thickness of the gate insulating film of the first transistor.

Abstract: Provided is a light detection device which allows influence on adjacent pixels to be reduced. The light detection device includes a first substrate portion, a second substrate portion, and a through via. The first substrate portion has a pixel configured to photoelectrically convert incident light. The second substrate portion has a readout circuit configured to output a pixel signal based on charge output from the pixel to a signal line. The through via configured to connect the first substrate portion and the second substrate portion. The pixel has a floating diffusion configured to temporarily retain charge generated by photoelectric conversion. The readout circuit has a first pixel transistor connected to the floating diffusion through the through via and a second pixel transistor connected to the first pixel transistor and the signal line.

Abstract: A solid-state imaging device is provided that enables miniaturization of a pixel and improvement in electrical properties of a transistor of a pixel circuit. The solid-state imaging device includes a first semiconductor layer and a second semiconductor layer. In the first semiconductor layer, a pixel including a photoelectric converter is arranged in a matrix along a plane direction. The number of the pixel is two or more. The second semiconductor layer is stacked on the first semiconductor layer on an opposite side to a light-incoming side of the pixel. In the second semiconductor layer, a first transistor electrically coupled to the pixel is provided. A gate lengthwise direction of the first transistor is inclined with respect to an arrangement direction of the pixel.

Abstract: A complementary transistor is constituted of a first transistor TR1 and a second transistor TR2, active regions 32, 42 of the respective transistors are formed by layering first A layers 33, 43 and the first B layers 35, 45 respectively, surface regions 201, 202 provided in a base correspond to first A layers 33, 43 respectively, first B layers 35, 45 each have a conductivity type different from that of the first A layers 33, 43, and extension layers 36, 46 of the first B layer are provided on insulation regions 211,212 respectively.

Abstract: A complementary transistor is constituted of a first transistor TR1 and a second transistor TR2, active regions 32, 42 of the respective transistors are formed by layering first A layers 33, 43 and the first B layers 35, 45 respectively, surface regions 201, 202 provided in a base correspond to first A layers 33, 43 respectively, first B layers 35, 45 each have a conductivity type different from that of the first A layers 33, 43, and extension layers 36, 46 of the first B layer are provided on insulation regions 211,212 respectively.

Abstract: The disclosed device reduces noise while suppressing an increase in layout area of transistors included in a readout circuit. This solid-state imaging device includes: a first substrate section; a second substrate section disposed on one side of the first substrate section; a readout circuit; and first and second transistor cells each having, for each readout circuit, a plurality of transistors included in the readout circuit, the first and second transistor cells being arranged adjacent to each other. In addition, the plurality of transistors includes amplification transistors, a sensor pixel is provided on the first substrate section, the readout circuit and the first and second transistor cells are provided on the second substrate section, the amplification transistors of the first and second transistor cells are arranged adjacent to each other, and a first main electrode region of a pair of main electrode regions of each of the amplification transistors is shared.

Abstract: A complementary transistor is constituted of a first transistor TR1 and a second transistor TR2, active regions 32, 42 of the respective transistors are formed by layering first A layers 33, 43 and the first B layers 35, 45 respectively, surface regions 201, 202 provided in a base correspond to first A layers 33, 43 respectively, first B layers 35, 45 each have a conductivity type different from that of the first A layers 33, 43, and extension layers 36, 46 of the first B layer are provided on insulation regions 211,212 respectively.

Abstract: A complementary transistor is constituted of a first transistor TR1 and a second transistor TR2, active regions 32, 42 of the respective transistors are formed by layering first A layers 33, 43 and the first B layers 35, 45 respectively, surface regions 201, 202 provided in a base correspond to first A layers 33, 43 respectively, first B layers 35, 45 each have a conductivity type different from that of the first A layers 33, 43, and extension layers 36, 46 of the first B layer are provided on insulation regions 211, 212 respectively.

Abstract: Provided is a semiconductor device, a measurement device, a measurement method, and a semiconductor system that enable accurate measurement of the plasma induced damage (PID) effect on a small scale. The semiconductor device includes an NMOSFET whose gate is connected to an antenna part that functions as an antenna in a plasma process and a PMOSFET that controls the connection between the NMOSFET and a ring oscillator. The semiconductor device is provided with a test element group (TEG) that includes an NMOSFET whose gate is connected to an antenna part that functions as an antenna in a plasma process and a PMOSFET that controls the connection between the NMOSFET and a ring oscillator.

Abstract: A complementary transistor is constituted of a first transistor TR1 and a second transistor TR2, active regions 32, 42 of the respective transistors are formed by layering first A layers 33, 43 and the first B layers 35, 45 respectively, surface regions 201, 202 provided in a base correspond to first A layers 33, 43 respectively, first B layers 35, 45 each have a conductivity type different from that of the first A layers 33, 43, and extension layers 36, 46 of the first B layer are provided on insulation regions 211, 212 respectively.

Abstract: A complementary transistor is constituted of a first transistor TR1 and a second transistor TR2, active regions 32, 42 of the respective transistors are formed by layering first A layers 33, 43 and the first B layers 35, 45 respectively, surface regions 201, 202 provided in a base correspond to first A layers 33, 43 respectively, first B layers 35, 45 each have a conductivity type different from that of the first A layers 33, 43, and extension layers 36, 46 of the first B layer are provided on insulation regions 211,212 respectively.

Abstract: The present technology relates to a solid state imaging device that enables a reduction in the manufacturing cost of the solid state imaging device, and an electronic apparatus. A first substrate including a pixel circuit having a pixel array unit and a second substrate including a first and a second signal processing circuit arranged side by side across a scribe area are stacked. The second substrate includes a first moisture-resistant ring surrounding at least part of a periphery of the first signal processing circuit, a second moisture-resistant ring surrounding at least part of a periphery of the second signal processing circuit, a third moisture-resistant ring surrounding at least part of a periphery of the second substrate in a layer different from the first and second moisture-resistant rings, and a barrier unit separating a first area between the first and second moisture-resistant rings and a second area.

Abstract: A complementary transistor is constituted of a first transistor TR1 and a second transistor TR2, active regions 32, 42 of the respective transistors are formed by layering first A layers 33, 43 and the first B layers 35, 45 respectively, surface regions 201, 202 provided in a base correspond to first A layers 33, 43 respectively, first B layers 35, 45 each have a conductivity type different from that of the first A layers 33, 43, and extension layers 36, 46 of the first B layer are provided on insulation regions 211,212 respectively.

Abstract: The present technology relates to a solid state imaging device that enables a reduction in the manufacturing cost of the solid state imaging device, and an electronic apparatus. A first substrate including a pixel circuit having a pixel array unit and a second substrate including a first and a second signal processing circuit arranged side by side across a scribe area are stacked. The second substrate includes a first moisture-resistant ring surrounding at least part of a periphery of the first signal processing circuit, a second moisture-resistant ring surrounding at least part of a periphery of the second signal processing circuit, a third moisture-resistant ring surrounding at least part of a periphery of the second substrate in a layer different from the first and second moisture-resistant rings, and a barrier unit separating a first area between the first and second moisture-resistant rings and a second area.

Abstract: The present disclosure relates to a semiconductor device, a measurement device, a measurement method, and a semiconductor system that enable accurate measurement of the plasma induced damage (PID) effect on a small scale. The semiconductor device includes: an NMOSFET whose gate is connected to an antenna part that functions as an antenna in a plasma process; and a PMOSFET that controls the connection between the NMOSFET and a ring oscillator. For example, the present disclosure can be applied to a semiconductor device or the like provided with a test element group (TEG) including: an NMOSFET whose gate is connected to an antenna part that functions as an antenna in a plasma process; and a PMOSFET that controls the connection between the NMOSFET and a ring oscillator.

Abstract: The present technology relates to a solid state imaging device that enables a reduction in the manufacturing cost of the solid state imaging device, and an electronic apparatus. A first substrate including a pixel circuit having a pixel array unit and a second substrate including a first and a second signal processing circuit arranged side by side across a scribe area are stacked. The second substrate includes a first moisture-resistant ring surrounding at least part of a periphery of the first signal processing circuit, a second moisture-resistant ring surrounding at least part of a periphery of the second signal processing circuit, a third moisture-resistant ring surrounding at least part of a periphery of the second substrate in a layer different from the first and second moisture-resistant rings, and a barrier unit separating a first area between the first and second moisture-resistant rings and a second area.

Abstract: The present disclosure relates to a solid-state image sensor capable of suppressing deterioration of the noise characteristics and the dark characteristics when capturing an image of radiation, a manufacturing method, and a radiation imaging device. A scintillator converts radiation to visible light. Pixels each including a photodiode are formed in a semiconductor substrate. The photodiode photoelectrically converts the visible light that has been converted by the scintillator. Only a silicon oxide film or a negative fixed charge film is formed on the substrate in an element isolation area of the pixel. The present disclosure can be applied to, for example, a radiation imaging device that captures an image of an X-ray with which an object is irradiated.

Abstract: Provided is a gas sensor that needs no temperature sensor for detecting a temperature of a heater for preventing dew condensation. The gas sensor comprises a hydrogen sensor 1 including: an element housing 13 having a detection chamber 13a to which hydrogen is introduced; a detection element 31 arranged in the detection chamber 13a and detecting hydrogen; a heater 21 for heating the detection chamber 13a by heat generation via passing an electric current through the heater 21, a resistance value of the heater 21 being changed corresponding to a temperature of the detection chamber 13a; and a microcomputer 51 and a heater operation circuit 52 for controlling the heater 21. Herein, the microcomputer 51 controls a temperature of the detection chamber 13a by adjusting the electric current passing through the heater 21 based on the resistance value of the heater 21.

Abstract: A mask pattern design method includes: dividing design layout data for a pattern into multiple regions and extracting any region wherein transfer dimensions obtained from a transfer simulation of the pattern from the plurality of regions exceeds a predetermined allowance range; setting a process window of which multiple transfer conditions of the pattern data from the region extracted by the process are each changed, and computing transfer dimensions obtained from a transfer simulation with each transfer condition with the process window; and extracting the transfer conditions wherein the transfer dimension obtained from the transfer simulation with each transfer condition with the process window exceeds a predetermined allowance range, and computing yield from an occurrence probability regarding the transfer condition.