Abstract: A semiconductor memory device includes: a plurality of banks with electrically rewritable memory cells arranged therein, the banks being configured to be simultaneously accessible in such a manner that a data write operation into a bank and a data read operation for another bank are simultaneously performed; a write-use data bus commonly disposed for the plurality of banks; a read-use data bus commonly disposed for the plurality of banks; a write circuit connected to the write-use data bus; a read circuit connected to the read-use data bus; a bank address decoder circuit for decoding external bank address signals for bank selecting to output internal bank address signals, the bank address decoder circuit having such an address conversion function that one of plural kinds of address conversions between the external bank address signals and the internal bank address signals is selectable; and a rewrite control circuit for sequence controlling a data write operation for a bank selected by the bank address decode

Abstract: A semiconductor integrated circuit device includes a first memory cell array corresponding to bank 0, a second memory cell array corresponding to bank 1, first address transition signal generating circuits which detect transitions of input addresses and generate first address transition signals, a second address transition signal generating circuit which pre-detects an end of automatic execution of bank 0 or bank 1 and generates a second address transition signal, and a read start trigger output circuit. The read start trigger output circuit outputs a read start trigger signal on the basis of the first address transition signals and the second address transition signal.

Abstract: A semiconductor integrated circuit device includes a main cell array, a fuse cell array, main cell word lines arranged at the main cell array, and fuse cell word lines arranged at the fuse cell array. The fuse cell word lines are formed in a same direction as a direction of the main cell word lines.

Abstract: A semiconductor integrated circuit device includes fuse cells arranged at a fuse cell array, a fuse cell data program and erase circuit, a fuse cell data control circuit, and fuse data latch circuits. The fuse cells include erasable and programmable nonvolatile memory cells. The fuse cell data program and erase circuit programs fuse data to the memory cells and erases the fuse data from the memory cells. The fuse cell data control circuit controls read out timing of the fuse data stored in the memory cells based on a signal generated upon detection of power-on. The fuse data latch circuits latch the fuse data read out from the memory cells.

Abstract: A memory cell array 1 has the arrangement of a plurality of cores, each of which comprises one block or a set of a plurality of blocks, each block defining a range of memory cells serving as a unit of data erase. A core selecting part for selecting an optional number of cores to write/erase data is provided for writing data in memory cells in cores selected on the basis of a write command and for erasing data from selected blocks in cores selected on the basis of an erase command. Thus, there is realized a free core system capable of reading data out from memory cells in unselected cores while writing/erasing data in cores selected by the core selecting part.

Abstract: A semiconductor device has a memory cell array having the arrangement of a plurality of cores, each of which comprises one block or a set of a plurality of blocks, each block defining a range of memory cells serving as a unit of data erase. The semiconductor device has a bank setting memory circuit configured to select an optional number of cores of the cores as a first bank and to set the remaining cores as a second bank, so as to allow a data read operation to be carried out in one of the first and second banks while a data write or erase operation is carried out in the other of the first and second banks.

Abstract: Disclosed is a functional element for use in an electric, an electronic or an optical device, and a method for producing the same. The functional element comprises a substrate having on an upper surface thereof a plurality of metal oxide needles extending upwardly of the upper surface of the substrate, with their respective central axes arranged substantially in parallel with each other, wherein the needles have a specific average circle-based diameter and a specific average aspect ratio, and wherein the needles are present at a specific density at the upper surface of the substrate.

Abstract: A particulate trap that burns and removes particulate matters (particles, consisting mainly of carbon particles, contained in the exhaust gas of a diesel engine of a car) trapped by a filter without using a specifically provided heat source such as a burner or an electric heater even when the car is running in ordinary urban areas, i.e., when the exhaust gas is low in temperature. In the particulate trap, a catalytic converter 3, formed of a metallic porous body having a three-dimensional network structure, carrying an oxidizing catalyst is placed upstream of a filter 4 that traps particulate matters. The catalytic converter 3 oxidizes NO in the exhaust gas into NO2, which in turn burns and removes particulate matters trapped by the filter 4.

Abstract: A semiconductor device includes a state code register that stores a state code representing a present internal state. A state transition logic unit is configured to determine a state code for a next internal state to be transited in accordance with a predetermined logic, based on a state code provided from the state code register and an input command instructing transition to a required state, and to set the determined state code into the state code register with synchronizing an internal clock. An expected value register is configured to hold an internal state to be detected, as an expected value code and a comparing unit compares the state code set in the state code register by the state transition logic unit to the expected value code in the expected value register and supplying an equal state signal when they coincide.

Abstract: A semiconductor integrated circuit device includes nonvolatile memory cell, a source of the cell receiving a ground potential, and a gate of the cell receiving a first control signal; a transistor, a source of the transistor receiving a drain potential of the cell, and a gate of the transistor receiving a second control signal; and a controller. The controller receives a third control signal generated upon detection of power-on and outputs the first and second control signals. A potential of the first control signal changes from the ground potential to a potential different from the ground potential, which is maintained during a first period of time, and a potential of the second control signal changes from the ground potential to a potential different from the ground potential, which is maintained during a second period of time.

Abstract: A semiconductor integrated circuit device includes a first memory cell array corresponding to bank 0, a second memory cell array corresponding to bank 1, first address transition signal generating circuits which detect transitions of input addresses and generate first address transition signals, a second address transition signal generating circuit which pre-detects an end of automatic execution of bank 0 or bank 1 and generates a second address transition signal, and a read start trigger output circuit. The read start trigger output circuit outputs a read start trigger signal on the basis of the first address transition signals and the second address transition signal.

Abstract: A semiconductor memory device, which allows concurrent execution of a write/erase operation and a read operation, is provided for each core with a core busy output circuit which has a function of, at the start, end, suspending or resuming of a write/erase operation, setting the sequence in which a command to write into/erase or read from a core, a core select signal indicating whether or not the core has been selected, and a busy signal indicating that the core is in the write/erase mode are set or reset so that multiple selection of a core in a write/erase operation and a core in a read operation does not occur.

Abstract: An endoscope suitable for autoclave sterilization includes an insertion section having an objective lens section disposed at the extreme end thereof for focusing a subject image and an eyepiece section located on the base end side of the inserting section and including at least an eyepiece lens. an image guide fiber is disposed in the bundle for transmitting the subject image in an observation section focused by the objective lens section. An eyepiece lens unit is disposed in the eyepiece section, the eyepiece lens unit causing the eyepiece lens to confront the base end structure whose hermetic seal level is higher than the watertight seal level of the shell of the endoscope. A focus position changing means is disposed to the eyepiece lens unit to change the focus position of the eyepiece lens. The eyepiece section is so constructed and/or assembled that the autoclave sterilization process does not cause water vapor or the like to adversely affect the operability of the eyepiece section.

Abstract: A semiconductor integrated circuit device includes a nonvolatile memory cell, a source of the cell receiving a ground potential, and a gate of the cell receiving a first control signal; a transistor, a source of the transistor receiving a drain potential of the cell, and a gate of the transistor receiving a second control signal; and a controller. The controller receives a third control signal generated upon detection of power-on and outputs the first and second control signals. A potential of the first control signal changes from the ground potential to a potential different from the ground potential, which is maintained during a first period of time, and a potential of the second control signal changes from the ground potential to a potential different from the ground potential, which is maintained during a second period of time.

Abstract: A semiconductor memory device includes: a plurality of banks with electrically rewritable memory cells arranged therein, the banks being configured to be simultaneously accessible in such a manner that a data write operation into a bank and a data read operation for another bank are simultaneously performed; a write-use data bus commonly disposed for the plurality of banks; a read-use data bus commonly disposed for the plurality of banks; a write circuit connected to the write-use data bus; a read circuit connected to the read-use data bus; a bank address decoder circuit for decoding external bank address signals for bank selecting to output internal bank address signals, the bank address decoder circuit having such an address conversion function that one of plural kinds of address conversions between the external bank address signals and the internal bank address signals is selectable; and a rewrite control circuit for sequence controlling a data write operation for a bank selected by the bank address decode

Abstract: There is disclosed a semiconductor memory device including a memory cell array containing a plurality of banks each having one or more blocks, a data erase circuit configured to erase data from selected blocks in banks at a unit of block, and an automatic multi-block erase circuit configured to enable a data read circuit configured to read data from memory cells provided in one bank, when data erase operation for all erase-object blocks in the one bank is completed, while continuing a data erasing operation of a next erase-object block included in another bank.

Abstract: An endoscope includes an image pickup unit 30 having a solid-state image pickup device 32 such as a CCD on a tip end side of an elongate insertion section. This image pickup unit 30 constitutes a tip end side unit 36U and a rear end side unit 43U by conducting a surface treatment (metallization) to nonmetal members such as a tip end cover glass 31 and a rear end cover glass 35, and by airtight coupling surface-treated portions of the nonmetal members to metal members such as a tip end cover glass frame 36 and a rear end cover glass frame 43 by brazing using soldering, and constitutes an optical system unit 60 by airtight coupling the metal members to metal members of an insulating unit 38U formed by airtight coupling a pipe member 41 and a ring member 42 to an insulating frame 38 by welding.

Abstract: A memory cell array 1 has the arrangement of a plurality of cores, each of which comprises one block or a set of a plurality of blocks, each block defining a range of memory cells serving as a unit of data erase. A core selecting part for selecting an optional number of cores to write/erase data is provided for writing data in memory cells in cores selected on the basis of a write command and for erasing data from selected blocks in cores selected on the basis of an erase command. Thus, there is realized a free core system capable of reading data out from memory cells in unselected cores while writing/erasing data in cores selected by the core selecting part.

Abstract: A semiconductor memory device, which allows concurrent execution of a write/erase operation and a read operation, is provided for each core with a core busy output circuit which has a function of, at the start, end, suspending or resuming of a write/erase operation, setting the sequence in which a command to write into/erase or read from a core, a core select signal indicating whether or not the core has been selected, and a busy signal indicating that the core is in the write/erase mode are set or reset so that multiple selection of a core in a write/erase operation and a core in a read operation does not occur.

Abstract: An endoscope capable of being autoclaved in accordance with the present invention includes an insertion unit, an internal endoscope space, and contents. The insertion unit has a soft member, which is made of a soft polymeric material, as at least part of a casing thereof. The internal endoscope space includes the internal space of the insertion unit that is formed at a first sealing level at which the internal space is sealed in a watertight manner relative to an outside. The contents include at least one hermetically sealed unit composed of a plurality of airtight partition members and formed at a second sealing level higher than the first sealing level by joining the meeting portions of the airtight partition members using an airtight joining material. All or part of the airtight partition members is stowed in the internal endoscope space.