Patents by Inventor Hidetsugu Uchida
Hidetsugu Uchida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240144729Abstract: An information processing apparatus calculates a parameter for each of a plurality of layers included in a first neural network through machine learning using a plurality of image datasets each containing a human biometric image. The information processing apparatus generates a determination model of determining the authenticity of a human biometric image included in a received image dataset, by setting a parameter calculated for a first layer of the first neural network in the first layer included in a second neural network that includes the first layer and does not include a second layer.Type: ApplicationFiled: January 5, 2024Publication date: May 2, 2024Applicant: FUJITSU LIMITEDInventors: Lina SEPTIANA, Hidetsugu UCHIDA, Tomoaki MATSUNAMI
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Publication number: 20230274581Abstract: A determination method implemented by a computer, the determination method including: in response to acquiring a primary image captured by a camera, calculating, based on a size of a region of the subject, an estimated value of a distance to a subject that is specified and included in the primary image; acquiring a secondary image captured by the camera focused on a position according to the calculated estimated value; and determining, based on the acquired secondary image, whether the subject is a display object.Type: ApplicationFiled: May 5, 2023Publication date: August 31, 2023Applicant: FUJITSU LIMITEDInventor: Hidetsugu UCHIDA
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Publication number: 20230047264Abstract: An authentication method executed by a computer, the authentication method includes obtaining a captured image captured by a camera; selecting one facial image from a plurality of facial images based on a position of each of the plurality of facial images included in the captured image; referring to a memory that stores pieces of biometric information associated with the respective plurality of facial images; specifying a piece of the biometric information associated with a facial image in which a degree of similarity to the selected facial image satisfies a criterion; and performing, when biometric information detected by a sensor is received, authentication based on verification of the specified piece of the biometric information against the received biometric information.Type: ApplicationFiled: October 11, 2022Publication date: February 16, 2023Applicant: FUJITSU LIMITEDInventors: SOICHI HAMA, Takahiro Aoki, Hidetsugu Uchida
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Publication number: 20220383458Abstract: A control method for a computer to execute a process includes receiving a plurality of pieces of captured data of a person; generating weight information that indicates a weight applied to each of the plurality of pieces of captured data based on quality of each of the plurality of pieces of captured data and the number of the plurality of pieces of captured data; and applying, when representative data that represents the plurality of pieces of captured data is acquired from the plurality of pieces of captured data, an algorithm in which the smaller the weight indicated by the generated weight information, the smaller an influence of each of the plurality of pieces of captured data on a calculation result of the representative data.Type: ApplicationFiled: August 3, 2022Publication date: December 1, 2022Applicant: FUJITSU LIMITEDInventor: Hidetsugu Uchida
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Publication number: 20220222961Abstract: An attribute determination device includes a memory and a processor coupled to the memory and the processor is configured to acquire images captured by a plurality of image capturing devices configured to capture the images, extract an image in which a first object which is an object whose attribute is to be determined appears, analyze the image of the first object appearing in the extracted image, calculate a first probability that the first object has a first attribute for each of a first image capturing devices that have captured the image in which the first object appears, and determine whether the first object has the first attribute based on a second probability and the first probability, the second probability being a probability for each of the plurality of image capturing devices and indicating a probability that an object having the first attribute appears in a captured image.Type: ApplicationFiled: March 30, 2022Publication date: July 14, 2022Applicant: FUJITSU LIMITEDInventor: Hidetsugu UCHIDA
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Publication number: 20210263923Abstract: An information processing device includes: a memory; and a processor coupled to the memory and configured to: store each first code binarized corresponding to a plurality of first media data; and calculate, based on a probability that a second code obtained by binarizing a feature vector corresponding to second media data is converted into the first code, each similarity between the second media data and each of the first media data.Type: ApplicationFiled: May 10, 2021Publication date: August 26, 2021Applicant: FUJITSU LIMITEDInventor: Hidetsugu Uchida
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Publication number: 20210216617Abstract: A biometric authentication device includes: a first memory; and a processor configured to: acquire an image that includes a face of one or more persons; specify a region that a face of a head person of a waiting line in which the one or more persons line up appears from the acquired image; extract feature of the face of the head person included in the specified region; select, by a first collation process of collating the extracted feature with feature indicating facial characteristics of persons and biometric information of each person, a group of persons similar to the head person among the persons; acquire the biometric information of the head person; and authenticate the head person by a second collation process of collating the biometric information of each person included in the group among the biometric information with the acquired biometric information of the head person.Type: ApplicationFiled: March 31, 2021Publication date: July 15, 2021Applicant: FUJITSU LIMITEDInventors: SATOSHI SEMBA, NARISHIGE ABE, SHIGEFUMI YAMADA, Tomoaki Matsunami, Kazuya UNO, Junji TAKAGI, Hidetsugu Uchida
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Patent number: 11010598Abstract: A biometric authentication device includes a memory and a processor configured to obtain a first biometric image of a target for authentication, identify a first feature quantity set including a first pixel feature quantity of the first biometric image and a first coordinate feature quantity of the first biometric image, perform calculation of a degree of similarity between a first person factor vector of the first biometric image and a second person factor vector of a template in accordance with the first feature quantity set, a pixel feature quantity of the template, and a coordinate feature quantity of the template, and perform an authentication process of the first biometric image in accordance with the calculated degree of similarity.Type: GrantFiled: May 15, 2019Date of Patent: May 18, 2021Assignee: FUJITSU LIMITEDInventor: Hidetsugu Uchida
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Patent number: 10680068Abstract: A technique related to a bonded semiconductor substrate capable of reducing an interface resistance is provided. The semiconductor substrate comprises a single-crystalline SiC substrate and a polycrystalline SiC substrate. The single-crystalline SIC substrate and the polycrystalline SiC substrate are bonded. A bonded region of the single-crystalline SiC substrate and the polycrystalline SiC substrate contains 1×1021 (atoms/cm3) or more of particular atoms.Type: GrantFiled: July 13, 2017Date of Patent: June 9, 2020Assignee: SICOXS CORPORATIONInventors: Ko Imaoka, Takanori Murasaki, Toshihisa Shimo, Hidetsugu Uchida, Akiyuki Minami
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Publication number: 20200006493Abstract: A technique related to a bonded semiconductor substrate capable of reducing an interface resistance is provided. The semiconductor substrate comprises a single-crystalline SiC substrate and a polycrystalline SiC substrate. The single-crystalline SIC substrate and the polycrystalline SiC substrate are bonded. A bonded region of the single-crystalline SiC substrate and the polycrystalline SiC substrate contains 1×1021 (atoms/cm3) or more of particular atoms.Type: ApplicationFiled: July 13, 2017Publication date: January 2, 2020Applicant: SICOXS CORPORATIONInventors: Ko IMAOKA, Takanori MURASAKI, Toshihisa SHIMO, Hidetsugu UCHIDA, Akiyuki MINAMI
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Publication number: 20190362136Abstract: A biometric authentication device includes a memory and a processor configured to obtain a first biometric image of a target for authentication, identify a first feature quantity set including a first pixel feature quantity of the first biometric image and a first coordinate feature quantity of the first biometric image, perform calculation of a degree of similarity between a first person factor vector of the first biometric image and a second person factor vector of a template in accordance with the first feature quantity set, a pixel feature quantity of the template, and a coordinate feature quantity of the template, and perform an authentication process of the first biometric image in accordance with the calculated degree of similarity.Type: ApplicationFiled: May 15, 2019Publication date: November 28, 2019Applicant: FUJITSU LIMITEDInventor: Hidetsugu Uchida
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Patent number: 9773678Abstract: A method for manufacturing a semiconductor substrate may comprise irradiating a surface of a first semiconductor layer and a surface of a second semiconductor layer with one or more types of first impurity in a vacuum. The method may comprise bonding the surface of the first semiconductor layer and the surface of the second semiconductor layer to each other in the vacuum. The method may comprise applying heat treatment to the semiconductor substrate produced in the bonding. The first impurity may be an inert impurity that does not generate carriers in the first and second semiconductor layers. The heat treatment may be applied such that a width of an in-depth concentration profile of the first impurity contained in the first and second semiconductor layers is narrower after execution of the heat treatment than before the execution of the heat treatment.Type: GrantFiled: July 9, 2015Date of Patent: September 26, 2017Assignees: KABUSHIKI KAISHA TOYOTA JIDOSHOKKI, SICOXS CORPORATIONInventors: Ko Imaoka, Motoki Kobayashi, Hidetsugu Uchida, Kuniaki Yagi, Takamitsu Kawahara, Naoki Hatta, Akiyuki Minami, Toyokazu Sakata, Tomoatsu Makino, Mitsuharu Kato
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Patent number: 9761479Abstract: A technique disclosed herein relates to a manufacturing method for a semiconductor substrate having the bonded interface with high bonding strength without forming an oxide layer at the bonded interface also for the substrate having surface that is hardly planarized. The manufacturing method for the semiconductor substrate may include an amorphous layer formation process in which a first amorphous layer is formed by modifying a surface of a support substrate and a second amorphous layer is formed by modifying a surface of a single-crystalline layer of a semiconductor. The manufacturing method may include a contact process in which the first amorphous layer and the second amorphous layer are contacted with each other. The manufacturing method may include a heat treatment process in which the support substrate and single-crystalline layer are heat-treated with the first amorphous layer and the second amorphous layer being in contact with each other.Type: GrantFiled: July 3, 2014Date of Patent: September 12, 2017Assignees: KABUSHIKI KAISHA TOYOTA JIDOSHOKKI, SICOXS CORPORATION, NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGYInventors: Ko Imaoka, Motoki Kobayashi, Hidetsugu Uchida, Kuniaki Yagi, Takamitsu Kawahara, Naoki Hatta, Akiyuki Minami, Toyokazu Sakata, Tomoatsu Makino, Hideki Takagi, Yuuichi Kurashima
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Publication number: 20170213735Abstract: A method for manufacturing a semiconductor substrate may comprise irradiating a surface of a first semiconductor layer and a surface of a second semiconductor layer with one or more types of first impurity in a vacuum. The method may comprise bonding the surface of the first semiconductor layer and the surface of the second semiconductor layer to each other in the vacuum. The method may comprise applying heat treatment to the semiconductor substrate produced in the bonding. The first impurity may be an inert impurity that does not generate carriers in the first and second semiconductor layers. The heat treatment may be applied such that a width of an in-depth concentration profile of the first impurity contained in the first and second semiconductor layers is narrower after execution of the heat treatment than before the execution of the heat treatment.Type: ApplicationFiled: July 9, 2015Publication date: July 27, 2017Applicants: KABUSHIKI KAISHA TOYOTA JIDOSHOKKI, SICOXS CORPORATIONInventors: Ko IMAOKA, Motoki KOBAYASHI, Hidetsugu UCHIDA, Kuniaki YAGI, Takamitsu KAWAHARA, Naoki HATTA, Akiyuki MINAMI, Toyokazu SAKATA, Tomoatsu MAKINO, Mitsuharu KATO
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Publication number: 20160322219Abstract: A semiconductor substrate including plural types of semiconductor layers exposed at a surface thereof is provided. A semiconductor substrate includes: a supporting substrate; a single-crystal, first semiconductor layer disposed on a surface of the supporting substrate; a single-crystal, second semiconductor layer disposed on parts of a surface of the first semiconductor layer; and a single-crystal, third semiconductor layer disposed on those parts of the surface of the first semiconductor layer on which the second semiconductor layer is not disposed. The third semiconductor layer has a crystal orientation aligned with that of the first semiconductor layer and is made of the same material as the first semiconductor layer.Type: ApplicationFiled: December 25, 2014Publication date: November 3, 2016Inventors: Ko IMAOKA, Hidetsugu UCHIDA, Jun SUDA
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Publication number: 20160204023Abstract: A technique disclosed herein relates to a manufacturing method for a semiconductor substrate having the bonded interface with high bonding strength without forming an oxide layer at the bonded interface also for the substrate having surface that is hardly planarized. The manufacturing method for the semiconductor substrate may include an amorphous layer formation process in which a first amorphous layer is formed by modifying a surface of a support substrate and a second amorphous layer is formed by modifying a surface of a single-crystalline layer of a semiconductor. The manufacturing method may include a contact process in which the first amorphous layer and the second amorphous layer are contacted with each other. The manufacturing method may include a heat treatment process in which the support substrate and single-crystalline layer are heat-treated with the first amorphous layer and the second amorphous layer being in contact with each other.Type: ApplicationFiled: July 3, 2014Publication date: July 14, 2016Applicants: KABUSHIKI KAISHA TOYOTA JIDOSHOKKI, SICOXS CORPORATION, NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGYInventors: Ko IMAOKA, Motoki KOBAYASHI, Hidetsugu UCHIDA, Kuniaki YAGI, Takamitsu KAWAHARA, Naoki HATTA, Akiyuki MINAMI, Toyokazu SAKATA, Tomoatsu MAKINO, Hideki TAKAGI, Yuuichi KURASHIMA
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Patent number: 7879657Abstract: An insulating film layer is formed between a channel region of an MOS element formed in a monocrystal silicon layer of an SOS substrate in which the monocrystal silicon layer is laminated on a sapphire substrate, and the sapphire substrate, thereby to bring a stress state of the monocrystal silicon layer on the insulating film layer into a tensile stress state.Type: GrantFiled: June 20, 2005Date of Patent: February 1, 2011Assignee: Oki Semiconductor Co., Ltd.Inventor: Hidetsugu Uchida
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Publication number: 20090090919Abstract: A semiconductor device includes a silicon carbide substrate having a channel region formed on a surface thereof; a silicon layer formed on the channel region; a gate insulation film formed on the silicon layer; and a gate electrode formed on the gate insulation film. A method of producing a semiconductor device includes the steps of: forming a silicon layer on a surface of a silicon carbide substrate; forming a gate insulation film on the silicon layer to form a laminated structure of the silicon layer and the gate insulation film; and forming a gate electrode on the gate insulation film.Type: ApplicationFiled: September 4, 2008Publication date: April 9, 2009Inventor: Hidetsugu Uchida
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Publication number: 20060079031Abstract: An insulating film layer is formed between a channel region of an MOS element formed in a monocrystal silicon layer of an SOS substrate in which the monocrystal silicon layer is laminated on a sapphire substrate, and the sapphire substrate, thereby to bring a stress state of the monocrystal silicon layer on the insulating film layer into a tensile stress state.Type: ApplicationFiled: June 20, 2005Publication date: April 13, 2006Inventor: Hidetsugu Uchida
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Patent number: 6524968Abstract: A method for forming an insulating film is provided which is capable of inhibiting spontaneous growth of a silicon oxide film formed on a silicon substrate and an increase in thickness of a film caused by exposure to an atmosphere. After having allowed a silicon dioxide layer with a predetermined thickness to grow on a surface of a silicon crystal, a surface of the silicon dioxide is exposed to organic gas containing no hydroxyl group or is exposed to ammonia gas.Type: GrantFiled: October 5, 2001Date of Patent: February 25, 2003Assignee: Oki Electric Industry Co., Ltd.Inventors: Masashi Takahashi, Toshio Nagata, Yoshirou Tsurugida, Takashi Ohsako, Hirotaka Mori, Akihiko Ohara, Hidetsugu Uchida, Hiroaki Uchida, Katsuji Yoshida, Masahiro Takahashi