Patents by Inventor Hidetsugu Uchida

Hidetsugu Uchida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030008523
    Abstract: A method for forming an insulating film is provided which is capable of inhibiting spontaneous growth of a silicon oxide film formed on a silicon substrate and an increase in thickness of a film caused by exposure to an atmosphere.
    Type: Application
    Filed: October 5, 2001
    Publication date: January 9, 2003
    Inventors: Masashi Takahashi, Toshio Nagata, Yoshirou Tsurugida, Takashi Ohsako, Hirotaka Mori, Akihiko Ohara, Hidetsugu Uchida, Hiroaki Uchida, Katsuji Yoshida, Masahiro Takahashi
  • Patent number: 6229175
    Abstract: A nonvolatile memory includes a charge transfer layer, having a low barrier height, between the floating gate electrode and the control gate electrode. Accordingly, the nonvolatile memory avoids the problem in which the number of program and erasure cycles is decreased as a result of degradation of a tunnel oxide film.
    Type: Grant
    Filed: March 19, 1999
    Date of Patent: May 8, 2001
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Hidetsugu Uchida
  • Patent number: 6075270
    Abstract: A field effect transistor and a method for forming the field effect transistor are made up of a source region which is formed on the substrate, a drain region which is formed on the substrate, a stepped portion which is formed in the substrate between the source region and the drain region, a gate insulating film which is formed on the stepped portion of the substrate, and a gate electrode which is formed on the gate insulating film, wherein, a thickness of the gate insulating film near the drain region, which is less than that of the gate insulating film on a channel region defined in the substrate between the source region and the drain region. Accordingly, the field effect transistor and a method for forming the field effect transistor can prevent degradation of transistor characteristics because of a hot carrier effect.
    Type: Grant
    Filed: July 31, 1998
    Date of Patent: June 13, 2000
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Masao Okihara, Hidetsugu Uchida
  • Patent number: 6037588
    Abstract: In order to achieve a method for analyzing the compositional distribution of deposited film adhering to the internal surface of a contact hole having a diameter in the deep submicron order, primary ions 18 are radiated into the surface 12a of an insulating film 12 where the contact hole 14 is formed to generate secondary ions 20. The primary ions are radiated into the surface of the insulating film from a constant diagonal direction. Then, mass spectrometry is performed on the resulting secondary ions to detect the compositional distribution of the deposited film 16 formed at the internal surface of the contact hole. Thus, the compositional distribution of the deposited film is ascertained over the depth-wise direction of the contact hole.
    Type: Grant
    Filed: February 9, 1998
    Date of Patent: March 14, 2000
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Guo-Lin Liu, Hidetsugu Uchida, Izumi Aikawa, Naokatsu Ikegami, Norio Hirashita
  • Patent number: 4920391
    Abstract: In a semiconductor memory device formed on a semiconductor substrate (11), a first FET (21) is formed on a substrate. A first polysilicon film (13) serves as a gate electrode of this first FET (21). A second polysilicon film (16) is formed over the first polysilicon film (13), being separated by an insulating film (15). A third polysilicon film (20) is formed on the top and sides of the second polysilicon film (16). The third polysilicon film (20) has an impurity-doped region (19). A lower end (20a) of the third polysilicon film (20) is in contact with the first polysilicon film (13). The first, second and third polysilicon films (13, 16, 20) form a second FET (22), with the second polysilicon film (16) forming a gate electrode, and that part of the third polysilicon film (20) which is between the impurity-doped region (19) and the contacting end (20a) and adjacent to the second polysilicon film (16 ) forming a channel.
    Type: Grant
    Filed: April 3, 1989
    Date of Patent: April 24, 1990
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Hidetsugu Uchida
  • Patent number: 4907197
    Abstract: A non-volatile semiconductor memory device includes a semiconductor substrate, and a source and a drain of a MOS transistor formed on one surface of the semiconductor substrate and spaced about from each other. First, second and third gates are formed on one side of the substrate through an insulating film and between the source and the drain of the MOS transistor. This memory device has one transistor construction and can be fabricated simply and finely.
    Type: Grant
    Filed: July 12, 1988
    Date of Patent: March 6, 1990
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Hidetsugu Uchida