Patents by Inventor Hideyuki Doi

Hideyuki Doi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10697086
    Abstract: In forming of a silicon carbide layer, when an X axis indicates a first value representing, in percentage, a value obtained by dividing a flow rate of silane by a flow rate of hydrogen and a Y axis indicates a second value representing a flow rate of ammonia in sccm, the first value and the second value fall within a quadrangular region surrounded by first coordinates, second coordinates, third coordinates, and fourth coordinates in XY plane coordinates. The first coordinates are (0.05, 6.5×10?4). The second coordinates are (0.05, 4.5×10?3). The third coordinates are (0.22, 1.2×10?2). The fourth coordinates are (0.22, 1.3×10?1). After the forming of the silicon carbide layer, an average value of carrier concentration of the silicon carbide layer is more than or equal to 1×1015 cm?3 and less than or equal to 2×1016 cm?3.
    Type: Grant
    Filed: August 2, 2016
    Date of Patent: June 30, 2020
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Keiji Wada, Hideyuki Doi, Hironori Itoh
  • Patent number: 10612160
    Abstract: An epitaxial wafer includes a silicon carbide film having a first main surface. A groove portion is formed in the first main surface. The groove portion extends in one direction along the first main surface. Moreover, a width of the groove portion in the one direction is twice or more as large as a width of the groove portion in a direction perpendicular to the one direction. Moreover, a maximum depth of the groove portion from the first main surface is not more than 10 nm.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: April 7, 2020
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Taro Nishiguchi, Jun Genba, Hironori Itoh, Tomoaki Hatayama, Hideyuki Doi
  • Patent number: 10472736
    Abstract: An epitaxial wafer includes a silicon carbide film having a first main surface. A groove portion is formed in the first main surface. The groove portion extends in one direction along the first main surface. Moreover, a width of the groove portion in the one direction is twice or more as large as a width of the groove portion in a direction perpendicular to the one direction. Moreover, a maximum depth of the groove portion from the first main surface is not more than 10 nm.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: November 12, 2019
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Taro Nishiguchi, Jun Genba, Hironori Itoh, Tomoaki Hatayama, Hideyuki Doi
  • Publication number: 20180237942
    Abstract: In forming of a silicon carbide layer, when an X axis indicates a first value representing, in percentage, a value obtained by dividing a flow rate of silane by a flow rate of hydrogen and a Y axis indicates a second value representing a flow rate of ammonia in sccm, the first value and the second value fall within a quadrangular region surrounded by first coordinates, second coordinates, third coordinates, and fourth coordinates in XY plane coordinates. The first coordinates are (0.05, 6.5×10?4). The second coordinates are (0.05, 4.5×10?3). The third coordinates are (0.22, 1.2×10?2). The fourth coordinates are (0.22, 1.3×10?1). After the forming of the silicon carbide layer, an average value of carrier concentration of the silicon carbide layer is more than or equal to 1×1015 cm?3 and less than or equal to 2×1016 cm?3.
    Type: Application
    Filed: August 2, 2016
    Publication date: August 23, 2018
    Inventors: Keiji Wada, Hideyuki Doi, Hironori Itoh
  • Publication number: 20180233562
    Abstract: A silicon carbide epitaxial substrate includes: a silicon carbide single crystal substrate; and an epitaxial layer. The silicon carbide single crystal substrate has a diameter of not less than 100 mm. The epitaxial layer has a thickness of not less than 10 ?m. The epitaxial layer has a carrier concentration of not less than 1×1014 cm?3 and not more than 1×1016 cm?3. A ratio of a standard deviation of the carrier concentration in a plane of the epitaxial layer to an average value of the carrier concentration in the plane is not more than 10%. The epitaxial layer has a main surface. The main surface has an arithmetic mean roughness Sa of not more than 0.3 nm. An area density of pits originated from a threading screw dislocation is not more than 1000 cm?2. Each of the pits has a maximum depth of not less than 8 nm.
    Type: Application
    Filed: August 18, 2015
    Publication date: August 16, 2018
    Inventors: Taro NISHIGUCHI, Keiji WADA, Jun GENBA, Hironori ITOH, Hideyuki DOI, Kenji HIRATSUKA
  • Publication number: 20180209064
    Abstract: An epitaxial wafer includes a silicon carbide film having a first main surface. A groove portion is formed in the first main surface. The groove portion extends in one direction along the first main surface. Moreover, a width of the groove portion in the one direction is twice or more as large as a width of the groove portion in a direction perpendicular to the one direction. Moreover, a maximum depth of the groove portion from the first main surface is not more than 10 nm.
    Type: Application
    Filed: March 23, 2018
    Publication date: July 26, 2018
    Inventors: Taro Nishiguchi, Jun Genba, Hironori Itoh, Tomoaki Hatayama, Hideyuki Doi
  • Patent number: 9957641
    Abstract: An epitaxial wafer includes a silicon carbide film having a first main surface. A groove portion is formed in the first main surface. The groove portion extends in one direction along the first main surface. Moreover, a width of the groove portion in the one direction is twice or more as large as a width of the groove portion in a direction perpendicular to the one direction. Moreover, a maximum depth of the groove portion from the first main surface is not more than 10 nm.
    Type: Grant
    Filed: July 22, 2015
    Date of Patent: May 1, 2018
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Taro Nishiguchi, Jun Genba, Hironori Itoh, Tomoaki Hatayama, Hideyuki Doi
  • Publication number: 20160326668
    Abstract: An epitaxial wafer includes a silicon carbide film having a first main surface. A groove portion is formed in the first main surface. The groove portion extends in one direction along the first main surface. Moreover, a width of the groove portion in the one direction is twice or more as large as a width of the groove portion in a direction perpendicular to the one direction. Moreover, a maximum depth of the groove portion from the first main surface is not more than 10 nm.
    Type: Application
    Filed: July 22, 2015
    Publication date: November 10, 2016
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Taro Nishiguchi, Jun Genba, Hironori Itoh, Tomoaki Hatayama, Hideyuki Doi
  • Patent number: 9455464
    Abstract: Provided are a gas decomposition component, a method for producing a gas decomposition component, and a power generation apparatus. A gas decomposition component 10 includes a cylindrical-body MEA 7 including a first electrode 2 disposed on an inner-surface side, a second electrode 5 disposed on an outer-surface side, and a solid electrolyte 1 sandwiched between the first electrode and the second electrode; and a porous metal body 11s inserted on the inner-surface side of the cylindrical-body MEA and electrically connected to the first electrode, wherein the gas decomposition component further includes a porous conductive-paste-coated layer 11 g formed on an inner circumferential surface of the first electrode, and a metal mesh sheet 11 a disposed on an inner circumferential side of the conductive-paste-coated layer, and an electrical connection between the first electrode and the porous metal body is established through the conductive-paste-coated layer and the metal mesh sheet.
    Type: Grant
    Filed: April 6, 2016
    Date of Patent: September 27, 2016
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Chihiro Hiraiwa, Masatoshi Majima, Tetsuya Kuwabara, Tomoyuki Awazu, Naho Mizuhara, Toshio Ueda, Hideyuki Doi, Toshiyuki Kuramoto
  • Publication number: 20160218385
    Abstract: Provided are a gas decomposition component, a method for producing a gas decomposition component, and a power generation apparatus. A gas decomposition component 10 includes a cylindrical-body MEA 7 including a first electrode 2 disposed on an inner-surface side, a second electrode 5 disposed on an outer-surface side, and a solid electrolyte 1 sandwiched between the first electrode and the second electrode; and a porous metal body 11s inserted on the inner-surface side of the cylindrical-body MEA and electrically connected to the first electrode, wherein the gas decomposition component further includes a porous conductive-paste-coated layer 11 g formed on an inner circumferential surface of the first electrode, and a metal mesh sheet 11 a disposed on an inner circumferential side of the conductive-paste-coated layer, and an electrical connection between the first electrode and the porous metal body is established through the conductive-paste-coated layer and the metal mesh sheet.
    Type: Application
    Filed: April 6, 2016
    Publication date: July 28, 2016
    Inventors: Chihiro HIRAIWA, Masatoshi MAJIMA, Tetsuya KUWABARA, Tomoyuki AWAZU, Naho MIZUHARA, Toshio UEDA, Hideyuki DOI, Toshiyuki KURAMOTO
  • Patent number: 9325024
    Abstract: Provided are a gas decomposition component, a method for producing a gas decomposition component, and a power generation apparatus. A gas decomposition component 10 includes a cylindrical-body MEA 7 including a first electrode 2 disposed on an inner-surface side, a second electrode 5 disposed on an outer-surface side, and a solid electrolyte 1 sandwiched between the first electrode and the second electrode; and a porous metal body 11s inserted on the inner-surface side of the cylindrical-body MEA and electrically connected to the first electrode, wherein the gas decomposition component further includes a porous conductive-paste-coated layer 11g formed on an inner circumferential surface of the first electrode, and a metal mesh sheet 11a disposed on an inner circumferential side of the conductive-paste-coated layer, and an electrical connection between the first electrode and the porous metal body is established through the conductive-paste-coated layer and the metal mesh sheet.
    Type: Grant
    Filed: November 29, 2011
    Date of Patent: April 26, 2016
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Chihiro Hiraiwa, Masatoshi Majima, Tetsuya Kuwabara, Tomoyuki Awazu, Naho Mizuhara, Toshio Ueda, Hideyuki Doi, Toshiyuki Kuramoto
  • Patent number: 9132384
    Abstract: Provided are a gas decomposition component, a power generation apparatus including the gas decomposition component, and a method for decomposing a gas. A gas decomposition component includes a cylindrical MEA including a first electrode layer, a cylindrical solid electrolyte layer, and a second electrode layer in order from an inside toward an outside, in a layered structure; a first gas channel through which a first gas that is decomposed flows, the first gas channel being disposed inside the cylindrical MEA; and a second gas channel through which a second gas flows, the second gas channel being disposed outside the cylindrical MEA, wherein the gas decomposition component further includes a heater for heating the entirety of the component; and a preheating pipe through which the first gas to be introduced into the first gas channel passes beforehand to be preheated.
    Type: Grant
    Filed: October 21, 2011
    Date of Patent: September 15, 2015
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Chihiro Hiraiwa, Masatoshi Majima, Tetsuya Kuwabara, Tomoyuki Awazu, Naho Mizuhara, Toshio Ueda, Hideyuki Doi, Toshiyuki Kuramoto
  • Publication number: 20150233018
    Abstract: A silicon carbide epitaxial substrate having a main surface (second main surface) includes: a base substrate; and a silicon carbide epitaxial layer formed on the base substrate and including the main surface (second main surface), the second main surface having a surface roughness of 0.6 nm or less, a ratio of standard deviation of a nitrogen concentration in the silicon carbide epitaxial layer at a surface layer including the main surface (second main surface) within a plane of the silicon carbide epitaxial substrate to an average value of the nitrogen concentration in the silicon carbide epitaxial layer at the surface layer within the plane of the silicon carbide epitaxial substrate being 15% or less.
    Type: Application
    Filed: May 6, 2015
    Publication date: August 20, 2015
    Inventors: Jun Genba, Taro Nishiguchi, Hideyuki Doi, Akira Matsushima
  • Patent number: 9057147
    Abstract: A silicon carbide epitaxial substrate having a main surface (second main surface) includes: a base substrate; and a silicon carbide epitaxial layer formed on the base substrate and including the main surface (second main surface), the second main surface having a surface roughness of 0.6 nm or less, a ratio of standard deviation of a nitrogen concentration in the silicon carbide epitaxial layer at a surface layer including the main surface (second main surface) within a plane of the silicon carbide epitaxial substrate to an average value of the nitrogen concentration in the silicon carbide epitaxial layer at the surface layer within the plane of the silicon carbide epitaxial substrate being 15% or less.
    Type: Grant
    Filed: April 11, 2014
    Date of Patent: June 16, 2015
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Jun Genba, Taro Nishiguchi, Hideyuki Doi, Akira Matsushima
  • Publication number: 20150072100
    Abstract: A silicon carbide epitaxial substrate having a main surface (second main surface) includes: a base substrate; and a silicon carbide epitaxial layer formed on the base substrate and including the main surface (second main surface), the second main surface having a surface roughness of 0.6 nm or less, a ratio of standard deviation of a nitrogen concentration in the silicon carbide epitaxial layer at a surface layer including the main surface (second main surface) within a plane of the silicon carbide epitaxial substrate to an average value of the nitrogen concentration in the silicon carbide epitaxial layer at the surface layer within the plane of the silicon carbide epitaxial substrate being 15% or less.
    Type: Application
    Filed: April 11, 2014
    Publication date: March 12, 2015
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Jun Genba, Taro Nishiguchi, Hideyuki Doi, Akira Matsushima
  • Publication number: 20130260280
    Abstract: Provided are a gas decomposition component, a method for producing a gas decomposition component, and a power generation apparatus. A gas decomposition component 10 includes a cylindrical-body MEA 7 including a first electrode 2 disposed on an inner-surface side, a second electrode 5 disposed on an outer-surface side, and a solid electrolyte 1 sandwiched between the first electrode and the second electrode; and a porous metal body 11s inserted on the inner-surface side of the cylindrical-body MEA and electrically connected to the first electrode, wherein the gas decomposition component further includes a porous conductive-paste-coated layer 11g formed on an inner circumferential surface of the first electrode, and a metal mesh sheet 11a disposed on an inner circumferential side of the conductive-paste-coated layer, and an electrical connection between the first electrode and the porous metal body is established through the conductive-paste-coated layer and the metal mesh sheet.
    Type: Application
    Filed: November 29, 2011
    Publication date: October 3, 2013
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Chihiro Hiraiwa, Masatoshi Majima, Tetsuya Kuwabara, Tomoyuki Awazu, Naho Mizuhara, Toshio Ueda, Hideyuki Doi, Toshiyuki Kuramoto
  • Publication number: 20130224612
    Abstract: Provided are a gas decomposition component, a power generation apparatus including the gas decomposition component, and a method for decomposing a gas. A gas decomposition component includes a cylindrical MEA including a first electrode layer, a cylindrical solid electrolyte layer, and a second electrode layer in order from an inside toward an outside, in a layered structure; a first gas channel through which a first gas that is decomposed flows, the first gas channel being disposed inside the cylindrical MEA; and a second gas channel through which a second gas flows, the second gas channel being disposed outside the cylindrical MEA, wherein the gas decomposition component further includes a heater for heating the entirety of the component; and a preheating pipe through which the first gas to be introduced into the first gas channel passes beforehand to be preheated.
    Type: Application
    Filed: October 21, 2011
    Publication date: August 29, 2013
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Chihiro Hiraiwa, Masatoshi Majima, Tetsuya Kuwabara, Tomoyuki Awazu, Naho Mizuhara, Toshio Ueda, Hideyuki Doi, Toshiyuki Kuramoto
  • Publication number: 20130171542
    Abstract: A gas decomposition component includes a cylindrical membrane electrode assembly (MEA) including a first electrode layer, a cylindrical solid electrolyte layer, and a second electrode layer in order from an inside toward an outside, in a layered structure, wherein an end portion of the cylindrical MEA is sealed, a gas guide pipe is inserted through another end portion of the cylindrical MEA into an inner space of the cylindrical MEA to form a cylindrical channel between the gas guide pipe and an inner circumferential surface of the cylindrical MEA, and a gas flowing through the gas guide pipe toward the sealed portion is made to flow out of the gas guide pipe in a region near the sealed portion so that a flow direction of the gas is reversed and the gas flows through the cylindrical channel in a direction opposite to the flow direction in the guide pipe.
    Type: Application
    Filed: October 13, 2011
    Publication date: July 4, 2013
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Chihiro Hiraiwa, Masatoshi Majima, Tetsuya Kuwabara, Tomoyuki Awazu, Naho Mizuhara, Toshio Ueda, Hideyuki Doi, Toshiyuki Kuramoto
  • Patent number: 7852896
    Abstract: A VCSEL includes a GaAs substrate; a first semiconductor distributed Bragg reflector (DBR) disposed on the GaAs substrate and including a first part and a second part on the first part; a semiconductor mesa disposed on the first semiconductor DBR and including an active layer; and a second DBR on the semiconductor mesa. The first part is composed of an undoped semiconductor material. The second part includes third III-V compound semiconductor layers composed of a material containing indium and gallium as the group III element and phosphorus as the group V element and fourth III-V compound semiconductor layers composed of a material containing gallium as the group III element and arsenic as the group V element. The third III-V compound semiconductor layers and the fourth III-V compound semiconductor layers are doped with an n-type impurity.
    Type: Grant
    Filed: May 8, 2009
    Date of Patent: December 14, 2010
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Yutaka Onishi, Hideyuki Doi
  • Publication number: 20100014551
    Abstract: A VCSEL includes a GaAs substrate; a first semiconductor distributed Bragg reflector (DBR) disposed on the GaAs substrate and including a first part and a second part on the first part; a semiconductor mesa disposed on the first semiconductor DBR and including an active layer; and a second DBR on the semiconductor mesa. The first part is composed of an undoped semiconductor material. The second part includes third III-V compound semiconductor layers composed of a material containing indium and gallium as the group III element and phosphorus as the group V element and fourth III-V compound semiconductor layers composed of a material containing gallium as the group III element and arsenic as the group V element. The third III-V compound semiconductor layers and the fourth III-V compound semiconductor layers are doped with an n-type impurity.
    Type: Application
    Filed: May 8, 2009
    Publication date: January 21, 2010
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Yutaka ONISHI, Hideyuki DOI