Patents by Inventor Hideyuki Kinoshita

Hideyuki Kinoshita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7674679
    Abstract: A manufacturing method of a semiconductor device disclosed herein, comprises: forming a first member to be patterned on a semiconductor substrate; patterning the first member to form a plurality of parallel linear patterns and a connecting portion which connects the linear patterns on at least one end side of the linear patterns; and removing the connecting portion.
    Type: Grant
    Filed: June 15, 2007
    Date of Patent: March 9, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hideyuki Kinoshita
  • Patent number: 7675161
    Abstract: A semiconductor device comprising a plurality of first wirings provided in a predetermined layer on a substrate with being lined up, and formed to extend longer or contract shorter from one side toward the other side along a direction in which the first wirings are lined up, adjacent one-end portions of the first wirings being arranged in positions displaced from one another in a direction crossing at right angles the direction in which the first wirings are lined up.
    Type: Grant
    Filed: December 27, 2005
    Date of Patent: March 9, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koji Hashimoto, Eiji Ito, Tetsuya Kamigaki, Hideyuki Kinoshita
  • Publication number: 20100046035
    Abstract: An information processing apparatus includes a first acquisition unit configured to acquire a frequency characteristic of a recording medium, a second acquisition unit configured to acquire a frequency characteristic of dot information, a dot density distribution calculation unit configured to calculate a dot density distribution based on the frequency characteristic of the recording medium and the frequency characteristic of the dot information, a correspondence generation unit configured to calculate a density of a binary image based on a density distribution of the binary image and the dot which corresponds to a halftone dot ratio and to generate a correspondence between the halftone dot ratio and the density, and a gradation correction generation unit configured to generate a gradation correction condition based on the correspondence between the halftone dot ratio and the density.
    Type: Application
    Filed: August 19, 2009
    Publication date: February 25, 2010
    Applicant: CANON KABUSHIKI KAISHA
    Inventor: Hideyuki Kinoshita
  • Publication number: 20100036354
    Abstract: The invention provides an absorbent article that is small and that can be easily worn by a user and a method for producing the absorbent article. The absorbent article that is used in abutment against a user's body includes: an absorbent body for absorbing fluid; and an absorbent-article main body whose face on a side close to the user's body in use is joined to the absorbent body. The absorbent body has a longitudinal direction, a width direction, and a thickness direction. One end section of the absorbent body in the longitudinal direction is undetachably joined to the absorbent-article main body, and another end section of the absorbent body in the longitudinal direction is detachably joined to a portion inside an outer edge of the absorbent-article main body. The absorbent body has a non-joined section that is not joined to the absorbent-article main body, between the joined section on a side close to the other end section and the outer edge of the absorbent-article main body.
    Type: Application
    Filed: November 6, 2007
    Publication date: February 11, 2010
    Applicant: UNI-CHARM CORPORATION
    Inventors: Jun Kudo, Hideyuki Kinoshita, Akira Hashino
  • Publication number: 20100010463
    Abstract: The invention includes an absorbent article 1 in which an undergarment 90 can be prevented from getting dirty with fluid that has been absorbed by an absorbent body 20, without a decrease in the amount of fluid that can be absorbed.
    Type: Application
    Filed: November 16, 2007
    Publication date: January 14, 2010
    Applicant: UNI-CHARM CORPORATION
    Inventors: Jun Kudo, Hideyuki Kinoshita, Akira Hashino
  • Patent number: 7626235
    Abstract: A NAND nonvolatile semiconductor memory device that has a memory cell array region and a selection gate region, has a semiconductor layer; a gate insulating film disposed on said semiconductor layer; a plurality of first electrode layers selectively disposed on said gate insulating film; a first device isolation insulating film formed in said memory cell array region and extends from between said adjacent first electrode layers into said semiconductor layer for device isolation; a second device isolation insulating film formed in said selection gate region and extends from between said adjacent first electrode layers into said semiconductor layer for device isolation; an interpoly insulating film formed at least on the top of said first electrode layers and said first device isolation insulating film in said memory cell array region; a second electrode layer disposed on said interpoly insulating film; and a third electrode layer disposed on said second electrode layer, said second device isolation insulating
    Type: Grant
    Filed: June 22, 2007
    Date of Patent: December 1, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hideyuki Kinoshita
  • Patent number: 7604926
    Abstract: A method of manufacturing a semiconductor device, comprises forming a first mask pattern on an under-layer region, forming a plurality of dummy-line patterns on the under-layer region, the dummy-line patterns being arranged at a first pitch, forming second mask patterns having mask parts provided on long sides of the dummy-line patterns, removing the dummy-line patterns, and etching the under-layer region by using the first mask pattern and the mask parts as a mask.
    Type: Grant
    Filed: February 3, 2006
    Date of Patent: October 20, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tetsuya Kamigaki, Eiji Ito, Koji Hashimoto, Hideyuki Kinoshita
  • Publication number: 20090096035
    Abstract: A method for manufacturing a semiconductor device has forming a first insulating film on a semiconductor substrate, forming an electrode layer on said first insulating film, etching said electrode layer, said first insulating film and said semiconductor substrate of a first predetermined region to form a trench, burying an element-isolating insulating film in said trench, forming a second insulating film on said element-isolating insulating film and above said electrode layer, etching said second insulating film, said electrode layer and said element-isolating insulating film of a second predetermined region to form a gate pattern and a dummy pattern, forming a third insulating film for covering said gate pattern and said dummy pattern, and planarizing said third insulating film using said second insulating film as a stopper.
    Type: Application
    Filed: October 15, 2008
    Publication date: April 16, 2009
    Inventor: Hideyuki KINOSHITA
  • Publication number: 20080191270
    Abstract: A NAND-type non-volatile semiconductor memory device has a semiconductor substrate, an element isolation insulating film which is formed on a surface of the semiconductor substrate spaced apart at a predetermined distance from each other, a first insulating film which is formed between the element isolation insulating films on the semiconductor substrate, a floating gate which is formed on the first insulating films, a second insulating gate which is formed on an end region of the floating gate, a control gate which is formed on the second insulating film, and a contact plug which is formed on a surface of the floating gate so that one end of the contact plug is electrically connected to the control gate.
    Type: Application
    Filed: February 1, 2008
    Publication date: August 14, 2008
    Inventor: Hideyuki KINOSHITA
  • Publication number: 20080020530
    Abstract: A manufacturing method of a semiconductor device disclosed herein, comprises: forming a first member to be patterned on a semiconductor substrate; forming a second member to be patterned on the first member; forming a third member to be patterned on the second member; patterning the third member to form a first line pattern and a first connecting portion in the third member, the first line pattern having a plurality of parallel linear patterns and the first connecting portion connecting the linear patterns on at least one end side of the linear patterns of the first line pattern; etching the second member with the third member as a mask to form a second line pattern and a second connecting portion in the second member, the second line pattern being the same pattern as the first line pattern and the second connecting portion being the same pattern as the first connecting portion; removing the second connecting portion of the second member; and etching the first member with the second member as a mask.
    Type: Application
    Filed: July 27, 2007
    Publication date: January 24, 2008
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Hideyuki Kinoshita
  • Publication number: 20080002470
    Abstract: A NAND nonvolatile semiconductor memory device that has a memory cell array region and a selection gate region, has a semiconductor layer; a gate insulating film disposed on said semiconductor layer; a plurality of first electrode layers selectively disposed on said gate insulating film; a first device isolation insulating film formed in said memory cell array region and extends from between said adjacent first electrode layers into said semiconductor layer for device isolation; a second device isolation insulating film formed in said selection gate region and extends from between said adjacent first electrode layers into said semiconductor layer for device isolation; an interpoly insulating film formed at least on the top of said first electrode layers and said first device isolation insulating film in said memory cell array region; a second electrode layer disposed on said interpoly insulating film; and a third electrode layer disposed on said second electrode layer, said second device isolation insulating
    Type: Application
    Filed: June 22, 2007
    Publication date: January 3, 2008
    Inventor: Hideyuki Kinoshita
  • Publication number: 20070238248
    Abstract: A manufacturing method of a semiconductor device disclosed herein, comprises: forming a first member to be patterned on a semiconductor substrate; patterning the first member to form a plurality of parallel linear patterns and a connecting portion which connects the linear patterns on at least one end side of the linear patterns; and removing the connecting portion.
    Type: Application
    Filed: June 15, 2007
    Publication date: October 11, 2007
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Hideyuki KINOSHITA
  • Patent number: 7247539
    Abstract: A manufacturing method of a semiconductor device disclosed herein, comprises: forming a first member to be patterned on a semiconductor substrate; patterning the first member to be patterned to form a plurality of parallel linear patterns and a connecting portion which connects the linear patterns on at least one end side of the linear patterns; and etching a region between the linear patterns and the connecting portion to separate the linear patterns and the connecting portion.
    Type: Grant
    Filed: January 13, 2005
    Date of Patent: July 24, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hideyuki Kinoshita
  • Publication number: 20070003881
    Abstract: A method of manufacturing a semiconductor device includes forming a plurality of dummy line patterns arranged at a first pitch on an underlying region, forming first mask patterns having predetermined mask portions formed on long sides of the dummy line patterns, each of the first mask patterns having a closed-loop shape and surrounding each of the dummy line patterns, removing the dummy line patterns, forming a second mask pattern having a first pattern portion which covers end portions of the first mask patterns and inter-end portions each located between adjacent ones of the end portions, etching the underlying region using the first mask patterns and the second mask pattern as a mask to form trenches each located between adjacent ones of the predetermined mask portions, and filling the trenches with a predetermined material.
    Type: Application
    Filed: June 15, 2006
    Publication date: January 4, 2007
    Inventors: Eiji Ito, Hideyuki Kinoshita, Tetsuya Kamigaki, Koji Hashimoto
  • Publication number: 20060237758
    Abstract: A semiconductor device includes a plurality of first active areas arranged in a first area including a first sub area, a second sub area located adjacent to the first sub area in a first direction, and a third sub area adjacent to the first sub area in a second direction perpendicular to the first direction, the plurality of first active areas extending in the second direction, having the same width and being partitioned by a plurality of first isolation areas having the same width, a second active area located in a second area located adjacent to the second sub area in the second direction and adjacent to the third sub area in the first direction, the second active area being wider than the first active area, and a plurality of control gate lines provided in the first and second sub areas and extending in the first direction.
    Type: Application
    Filed: April 25, 2006
    Publication date: October 26, 2006
    Inventor: Hideyuki Kinoshita
  • Publication number: 20060234165
    Abstract: A method of manufacturing a semiconductor device, comprises forming a first mask pattern on an under-layer region, forming a plurality of dummy-line patterns on the under-layer region, the dummy-line patterns being arranged at a first pitch, forming second mask patterns having mask parts provided on long sides of the dummy-line patterns, removing the dummy-line patterns, and etching the under-layer region by using the first mask pattern and the mask parts as a mask.
    Type: Application
    Filed: February 3, 2006
    Publication date: October 19, 2006
    Inventors: Tetsuya Kamigaki, Eiji Ito, Koji Hashimoto, Hideyuki Kinoshita
  • Publication number: 20060194429
    Abstract: A semiconductor device comprising a plurality of first wirings provided in a predetermined layer on a substrate with being lined up, and formed to extend longer or contract shorter from one side toward the other side along a direction in which the first wirings are lined up, adjacent one-end portions of the first wirings being arranged in positions displaced from one another in a direction crossing at right angles the direction in which the first wirings are lined up.
    Type: Application
    Filed: December 27, 2005
    Publication date: August 31, 2006
    Inventors: Koji Hashimoto, Eiji Ito, Tetsuya Kamigaki, Hideyuki Kinoshita
  • Publication number: 20060068578
    Abstract: A manufacturing method of a semiconductor device disclosed herein, comprises: forming a first member to be patterned on a semiconductor substrate; patterning the first member to be patterned to form a plurality of parallel linear patterns and a connecting portion which connects the linear patterns on at least one end side of the linear patterns; and etching a region between the linear patterns and the connecting portion to separate the linear patterns and the connecting portion.
    Type: Application
    Filed: January 13, 2005
    Publication date: March 30, 2006
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Hideyuki Kinoshita
  • Patent number: 6841233
    Abstract: The invention relates a source sheet for stencil printing comprising: a porous support material; a porous resin film formed on a surface of the porous support material; wherein, the porous support material has a maximum air permeability of 90 s/100 cc; and, the porous resin film has a maximum air permeability of 600 s/100 cc; preferably, the air permeability of the porous support material?the air permeability of the porous resin film. According to the source sheet and plate manufacturing method of the present invention, the plate for the stencil printing can be obtained which is superior in the pore block property and in which the thermal deformation of the source sheet during the plate manufacturing is suppressed.
    Type: Grant
    Filed: September 17, 2002
    Date of Patent: January 11, 2005
    Assignee: Riso Kagaku Corporation
    Inventors: Hideyuki Kinoshita, Yasuo Yamamoto, Tsutomu Nio, Toru Nakai, Yuichi Ogawa
  • Patent number: 6811866
    Abstract: A heat-sensitive stencil sheet is provided, which is inhibited from jamming at the time of carrying or creasing at the time of winding around a drum, and thus excellent in carrying property and winding property. This heat-sensitive stencil sheet comprises a laminate of a thermoplastic resin film and a porous substrate mainly composed of synthetic fibers, and satisfies 0.150≦T−H wherein T denotes an arithmetic average value (g·cm/cm) of absolute values of KES bending torque in lengthwise direction of the stencil sheet at curvatures of +2.3 and −2.3 cm−1, H denotes a bending hysteresis (g·cm/cm), and T−H denotes a residual torque (g·cm/cm).
    Type: Grant
    Filed: September 14, 1999
    Date of Patent: November 2, 2004
    Assignee: Riso Kagaku Corporation
    Inventors: Hideyuki Kinoshita, Hiroshi Watanabe