Patents by Inventor Hideyuki Sugiyama

Hideyuki Sugiyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10930988
    Abstract: A signal transmission cable includes a signal line, an insulation layer configured to cover the signal line, and a plating layer configured to cover the insulation layer. An arithmetic average roughness Ra of an outer peripheral surface of the insulation layer is between 0.6 ?m and 10 ?m inclusive. A method of manufacturing the signal transmission cable includes covering the signal line with the insulation layer, followed by conducting a dry-ice-blasting on the outer peripheral surface of the insulation layer, followed by conducting a corona discharge exposure process on the outer peripheral surface, and forming the plating layer on the outer peripheral surface.
    Type: Grant
    Filed: January 29, 2020
    Date of Patent: February 23, 2021
    Assignee: Hitachi Metals, Ltd.
    Inventors: Kazufumi Suenaga, Yuju Endo, Hideyuki Sagawa, Takahiro Sugiyama, Hiroshi Ishikawa
  • Publication number: 20210043338
    Abstract: A high frequency signal transmission cable includes a conductor, an insulator provided over a periphery of the conductor, a plating layer provided over a periphery of the insulator, and a sheath provided over a periphery of the plating layer. A crack suppressing layer includes a non-cross-linked polyethylene is provided between the insulator and the plating layer, in such a manner as to remain in contact with the insulator while being provided with the plating layer over an entire periphery of a roughened outer surface of the crack suppressing layer. The crack suppressing layer is unadhered to the insulator. The plating layer is adhered to the crack suppressing layer. The crack suppressing layer suppresses an occurrence of a cracking in the plating layer by bending together with the plating layer while being integral and moving with the plating layer in a longitudinal direction of the cable.
    Type: Application
    Filed: October 23, 2020
    Publication date: February 11, 2021
    Inventors: Detian HUANG, Yoshinori TSUKAMOTO, Masashi MORIYAMA, Hideyuki SAGAWA, Takahiro SUGIYAMA
  • Patent number: 10916281
    Abstract: According to one embodiment, a magnetic memory apparatus includes a first stacked body and a controller. The first stacked body includes a first magnetic layer, a first counter magnetic layer, and a first intermediate layer placed between the first magnetic layer and the first counter magnetic layer. The first intermediate layer is nonmagnetic. The controller is electrically connected to the first magnetic layer and the first counter magnetic layer. The controller is configured to perform a first operation of supplying first pulse current to the first stacked body. The first pulse current includes a first constant-current period. A first electrical resistance value of the first stacked body before the supply of the first pulse current is different from a second electrical resistance value of the first stacked body after the supply of the first pulse current.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: February 9, 2021
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideyuki Sugiyama, Kazutaka Ikegami, Naoharu Shimomura
  • Patent number: 10910133
    Abstract: A linear shape member is composed of a linear shape electrical insulating body comprising irregularities on a surface, and a plating layer coating the surface of the electrical insulating body. An average irregularities spacing Sm of the irregularities is not more than 20.0 ?m.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: February 2, 2021
    Assignee: HITACHI METALS, LTD.
    Inventors: Kazufumi Suenaga, Hideyuki Sagawa, Takahiro Sugiyama
  • Patent number: 10902900
    Abstract: A magnetic memory device includes a conductive member, a stacked body, and a controller. The stacked body includes a first magnetic layer, a second magnetic layer provided between the conductive member and the first magnetic layer, and a third magnetic layer stacked with the first magnetic layer and the second magnetic layer. The controller causes a current to flow in the conductive member. The controller causes a current to flow between the conductive member and the stacked body. The controller is able to identify three or more levels of an electrical resistance value of the stacked body.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: January 26, 2021
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsuhiko Koui, Hiroaki Yoda, Tomoaki Inokuchi, Naoharu Shimomura, Hideyuki Sugiyama
  • Patent number: 10896708
    Abstract: According to one embodiment, a magnetic memory device includes a conductive member, a first element portion, and a controller. The conductive member includes a first portion, a second portion, and a third portion between the first portion and the second portion. The first element portion includes a first element, a first interconnect, and a first circuit. The first element includes a first magnetic layer, a first counter magnetic layer, and a first nonmagnetic layer. The first counter magnetic layer is provided between the third portion and the first magnetic layer. The first nonmagnetic layer is provided between the first counter magnetic layer and the first magnetic layer. The first interconnect is electrically connected to the first magnetic layer. The first circuit is electrically connected to the first interconnect. The first circuit includes a first switch, a first capacitance element, a first parallel switch, and a first parallel capacitance element.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: January 19, 2021
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomoaki Inokuchi, Katsuhiko Koui, Naoharu Shimomura, Hideyuki Sugiyama, Kazutaka Ikegami, Susumu Takeda, Satoshi Takaya, Shinobu Fujita, Hiroaki Yoda
  • Publication number: 20210005351
    Abstract: A high frequency signal transmission cable includes a conductor, an insulator provided over a periphery of the conductor, a plating layer provided over a periphery of the insulator, and a sheath provided over a periphery of the plating layer. A crack suppressing layer is provided between the insulator and the plating layer, in such a manner as to remain in contact with the insulator while being provided with the plating layer over an outer surface of the crack suppressing layer. The crack suppressing layer suppresses the occurrence of a cracking in the plating layer by bending while moving in a longitudinal direction of the cable relative to a bending of the insulator.
    Type: Application
    Filed: October 8, 2019
    Publication date: January 7, 2021
    Inventors: Detian Huang, Yoshinori Tsukamoto, Masashi Moriyama, Hideyuki Sagawa, Takahiro Sugiyama
  • Patent number: 10873063
    Abstract: The present invention is conceived in such a way as to prevent any damage to the battery management unit even if the solution leaks out of the cell, providing the battery with high safety. The battery according to the present invention is characterized by being provided with a cell, a battery management unit for managing the cell, a protection case holding the battery management unit, and a housing containing the cell and the protection case, wherein the protection case inside is hermetically sealed.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: December 22, 2020
    Assignee: ELIIY POWER CO., LTD
    Inventors: Hideyuki Sugiyama, Hiroshi Sato, Takeshi Sawada, Kazutoshi Miyauchi
  • Patent number: 10867725
    Abstract: A high frequency signal transmission cable includes a conductor, an insulator provided over a periphery of the conductor, a plating layer provided over a periphery of the insulator, and a sheath provided over a periphery of the plating layer. A crack suppressing layer is provided between the insulator and the plating layer, in such a manner as to remain in contact with the insulator while being provided with the plating layer over an outer surface of the crack suppressing layer. The crack suppressing layer suppresses the occurrence of a cracking in the plating layer by bending while moving in a longitudinal direction of the cable relative to a bending of the insulator.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: December 15, 2020
    Assignee: HITACHI METALS, LTD.
    Inventors: Detian Huang, Yoshinori Tsukamoto, Masashi Moriyama, Hideyuki Sagawa, Takahiro Sugiyama
  • Patent number: 10818887
    Abstract: The present invention provides a power storage device capable of preventing deterioration of sealability even when a pulling force is applied to a casing and having high safety and excellent durability.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: October 27, 2020
    Assignees: Honda Motor Co., Ltd., ELIIY Power Co., Ltd.
    Inventors: Tomoya Makabe, Takeshi Yanagisawa, Hiroyuki Suzuki, Masaharu Nakamori, Hideyuki Sugiyama, Hiroshi Sato, Takeshi Sawada, Kazutoshi Miyauchi
  • Patent number: 10811067
    Abstract: According to one embodiment, a magnetic memory device includes a conductive layer, a first magnetic layer, a second magnetic layer, and a first nonmagnetic layer. The conductive layer includes first and second regions, and a third region between the first region and the second region. The second magnetic layer is provided between the third region and the first magnetic layer in a first direction crossing a second direction. The second direction is from the first region toward the second region. The first nonmagnetic layer is provided between the first and second magnetic layers. The second region includes first to third conductive portions. A direction from the first conductive portion toward the second conductive portion is aligned with a third direction. The third direction crosses a plane including the first and second directions. The third conductive portion is between the first and second conductive portions in the third direction.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: October 20, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Altansargai Buyandalai, Satoshi Shirotori, Yuichi Ohsawa, Hideyuki Sugiyama, Mariko Shimizu, Hiroaki Yoda, Katsuhiko Koui
  • Patent number: 10802610
    Abstract: A position pointer includes a signal generation circuit, which generates at least one signal. The position pointer in operation transmits the at least one signal to a sensor of a position detector. The position pointer includes a first electrode arranged to protrude from one end portion of a pen-shaped housing along an axial center direction and a second electrode including at least three electrode pieces disposed near the first electrode in such a manner as to surround a central axis of the housing. The at least three electrode pieces are electrically isolated from each other. The position pointer has a signal supply control circuit, which, in operation, controls supply of signals to selectively supply the at least one signal to the second electrode that includes the at least three electrode pieces and to the first electrode.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: October 13, 2020
    Assignee: Wacom Co., Ltd.
    Inventors: Hiroshi Munakata, Takashi Suzuki, Hideyuki Hara, Yoshihisa Sugiyama
  • Patent number: 10797229
    Abstract: According to one embodiment, a magnetic memory device includes a conductive layer, first to fourth magnetic layers, first and second intermediate layers, and a controller. The conductive layer includes first, to fifth portions. The first magnetic layer is separated from the third portion. The second magnetic layer is provided between the third portion and the first magnetic layer. The first intermediate layer is provided between the first and second magnetic layers. The third magnetic layer is separated from the fourth portion. The fourth magnetic layer is provided between the fourth portion and the third magnetic layer. The second intermediate layer is provided between the third and fourth magnetic layers. The controller is electrically connected to the first and second portions. The controller implements a first operation of supplying a first current to the conductive layer, and a second operation of supplying a second current to the conductive layer.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: October 6, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Altansargai Buyandalai, Satoshi Shirotori, Yuichi Ohsawa, Hideyuki Sugiyama, Mariko Shimizu, Hiroaki Yoda, Tomoaki Inokuchi
  • Patent number: 10770772
    Abstract: A signal transmission cable includes a signal line, an insulation layer configured to cover the signal line, and a plating layer configured to cover the insulation layer. An arithmetic average roughness Ra of an outer peripheral surface of the insulation layer is between 0.6 ?m and 10 ?m inclusive. A method of manufacturing the signal transmission cable includes covering the signal line with the insulation layer, followed by conducting a dry-ice-blasting on the outer peripheral surface of the insulation layer, followed by conducting a corona discharge exposure process on the outer peripheral surface, and forming the plating layer on the outer peripheral surface.
    Type: Grant
    Filed: July 2, 2018
    Date of Patent: September 8, 2020
    Assignee: Hitachi Metals, Ltd.
    Inventors: Kazufumi Suenaga, Yuju Endo, Hideyuki Sagawa, Takahiro Sugiyama, Hiroshi Ishikawa
  • Publication number: 20200279596
    Abstract: According to one embodiment, a magnetic memory device includes a conductive member, a first element portion, and a controller. The conductive member includes a first portion, a second portion, and a third portion between the first portion and the second portion. The first element portion includes a first element, a first interconnect, and a first circuit. The first element includes a first magnetic layer, a first counter magnetic layer, and a first nonmagnetic layer. The first counter magnetic layer is provided between the third portion and the first magnetic layer. The first nonmagnetic layer is provided between the first counter magnetic layer and the first magnetic layer. The first interconnect is electrically connected to the first magnetic layer. The first circuit is electrically connected to the first interconnect. The first circuit includes a first switch, a first capacitance element, a first parallel switch, and a first parallel capacitance element.
    Type: Application
    Filed: January 13, 2020
    Publication date: September 3, 2020
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tomoaki INOKUCHI, Katsuhiko KOUI, Naoharu SHIMOMURA, Hideyuki SUGIYAMA, Kazutaka IKEGAMI, Susumu TAKEDA, Satoshi TAKAYA, Shinobu FUJITA, Hiroaki YODA
  • Patent number: 10755836
    Abstract: A signal transmission cable includes: at least one conductor including at least one wire; a covering layer coating the at least one conductor, the covering layer being made of an insulator; a coating layer coating a periphery of the covering layer; and a plated layer coating the coating layer, the plated layer being made of a material including a metallic material.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: August 25, 2020
    Assignee: HITACHI METALS, LTD.
    Inventors: Hideyuki Sagawa, Takahiro Sugiyama, Kazufumi Suenaga, Hiroshi Ishikawa
  • Publication number: 20200255439
    Abstract: The present invention provides a compound having an MAGL inhibitory action, and expected to be useful as an agent for the prophylaxis or treatment of neurodegenerative diseases (e.g., Alzheimer's disease, Parkinson's disease, Huntington's disease, amyotrophic lateral sclerosis, traumatic brain injury, glaucoma, multiple sclerosis etc.), anxiety disorder, pains (e.g., inflammatory pain, cancerous pain, neurogenic pain etc.), epilepsy, depression and the like. The present invention relates to a compound represented by the formula (I): wherein each symbol is as defined in the description, or a salt thereof.
    Type: Application
    Filed: September 27, 2018
    Publication date: August 13, 2020
    Applicant: Takeda Pharmaceutical Company Limited
    Inventors: Makoto KAMATA, Hideyuki SUGIYAMA, Minoru NAKAMURA, Masataka MURAKAMI, Shuhei IKEDA, Tomohiro OKAWA, Hidekazu TOKUHARA
  • Patent number: 10734055
    Abstract: A memory device according to an embodiment includes: a plurality of memory cells including a storage element having a first and second terminals; a reference resistor having a third and fourth terminals; a first current source electrically connected to the first terminal of the storage element in the selected memory cell; a second current source electrically connected to the third terminal; and a determination circuit that determines the greater one among a resistance value of a storage element of selected one and a resistance value of the reference resistor, the resistance value of the reference resistor being smaller than a middle value between a mean value of first resistance values obtained from the storage elements in the high-resistance state and a mean value of second resistance values obtained from the storage elements in the low-resistance state, and greater than the mean value of the second resistance values.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: August 4, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideyuki Sugiyama, Naoharu Shimomura, Kazutaka Ikegami
  • Publication number: 20200243226
    Abstract: A linear shape member is composed of a linear shape electrical insulating body comprising irregularities on a surface, and a plating layer coating the surface of the electrical insulating body. An average irregularities spacing Sm of the irregularities is not more than 20.0 ?m.
    Type: Application
    Filed: January 9, 2020
    Publication date: July 30, 2020
    Inventors: Kazufumi SUENAGA, Hideyuki SAGAWA, Takahiro SUGIYAMA
  • Patent number: RE48334
    Abstract: The present invention relates to a compound represented by the formula wherein ring A is a nitrogen-containing heterocycle; ring B is an aromatic ring optionally having substituent(s); ring D is an aromatic ring optionally having substituent(s); L is a group represented by the formula R2, R3, R4a and R4b are each independently a hydrogen atom, an optionally halogenated C1-6 alkyl group or an optionally halogenated C3-6 cycloalkyl group, or R2 and R3 are optionally bonded via an alkylene chain or an alkenylene chain, or R4a and R4b are optionally bonded via an alkylene chain or an alkenylene chain; R1 is a hydrogen atom or a substituent; m and n are each independently an integer of 0 to 5; m+n is an integer of 2 to 5; and is a single bond or double bond, or a salt thereof; and the like.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: December 1, 2020
    Assignee: Takeda Pharmaceutical Company Limited
    Inventors: Junya Shirai, Hideyuki Sugiyama, Taku Kamei, Hironobu Maezaki