Patents by Inventor Hideyuki Unno

Hideyuki Unno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6759722
    Abstract: In the present semiconductor device, a chip with an LSI circuit is secured to a board 3 (with the chip flipped) so as to be level. The LSI circuit on the chip is specified to operate normally only when the chip is level. Further, the back of the chip is processed so as to give stress to the chip. The chip has a reduced thickness of 50 &mgr;m or less (alternatively 30 &mgr;m to 50 &mgr;m). Therefore, when the chip is detached from the board, it deforms and is no longer level due to the stress, which prohibits the LSI circuit from operating normally. This way, the present semiconductor device ensures that no analysis can be conducted on the LSI circuit once the chip is detached.
    Type: Grant
    Filed: March 30, 2001
    Date of Patent: July 6, 2004
    Assignees: Sharp Kabushiki Kaisha, Nippon Telegraph and Telephone Corporation
    Inventors: Eiji Yanagawa, Akihiko Nakano, Toshinori Ohmi, Hironori Matsumoto, Tadao Takeda, Hideyuki Unno, Hiroshi Ban
  • Patent number: 6545371
    Abstract: A semiconductor device includes, on a protective film laminated on a circuit principal part, (i) a light blocking film provided so as to cover the circuit principal part, (ii) an aluminum oxide film provided so as to completely cover the light blocking film, and (iii) a light-blocking upper wiring provided on the aluminum oxide film. An attempt to exfoliate the light blocking film or the light blocking upper wiring causes the resistance-detection-use upper wiring to break or thin, thereby resulting in an increase in the resistance of the resistance-detection-use wiring. The increase in the resistance is detected by the resistance detecting circuit part, and malfunction or inoperativeness of the circuit principal part is caused in response of detection. By so doing, the circuit principal part can be protected from analysis.
    Type: Grant
    Filed: April 16, 2001
    Date of Patent: April 8, 2003
    Assignees: Sharp Kabushiki Kaisha, Nippon Telegraph and Telephone Corporation
    Inventors: Hironori Matsumoto, Akihiko Nakano, Toshinori Ohmi, Eiji Yanagawa, Hideyuki Unno, Hiroshi Ban, Tadao Takeda
  • Patent number: 6472730
    Abstract: A semiconductor device in accordance with the present invention includes a semiconductor element chip pressed and secured on a distortion die-pad so that the semiconductor element chip, sealed inside a package, is held in a predetermined distorted state. The predetermined distorted state is preferably downward or upward warping. The semiconductor element chip operates normally in the distorted state, and does not operate normally when the semiconductor element chip is separated from the semiconductor device, and thereby released from the distortion and laid alone. This ensures that the semiconductor element chip is protected from circuit analysis.
    Type: Grant
    Filed: April 18, 2000
    Date of Patent: October 29, 2002
    Assignees: Sharp Kabushiki Kaisha, Nippon Telegraph and Telephone Corporation
    Inventors: Eiji Yanagawa, Akihiko Nakano, Toshinori Ohmi, Tadao Takeda, Hideyuki Unno, Hiroshi Ban
  • Publication number: 20020095588
    Abstract: An authentication token includes a personal collation unit and communication unit. The personal collation unit includes a sensor, storage unit, and collation unit. The sensor detects biometrical information of a user and outputs the detection result as sensing data. The storage unit stores in advance registered data to be collated with the biometrical information of the user. The collation unit collates the registered data with the sensing data and outputs the collation result as authentication data. The communication unit transmits the authentication data from the personal collation unit to the use device as communication data. The personal collation unit and communication unit are integrated.
    Type: Application
    Filed: May 11, 2001
    Publication date: July 18, 2002
    Inventors: Satoshi Shigematsu, Kenichi Saito, Katsuyuki Machida, Takahiro Hatano, Hakaru Kyuragi, Hideyuki Unno, Hiroki Suto, Mamoru Nakanishi, Koji Fujii, Hiroki Morimura, Toshishige Shimamura, Takuya Adachi, Namiko Ikeda
  • Patent number: 6303471
    Abstract: After a reinforcing plate is bonded to the lower surface of a semiconductor substrate having a major surface on which integrated circuits are formed, the reinforcing plate is cut in units of integrated circuit chips. A reinforcing member is formed from the reinforcing plate bonded to the lower surface of each integrated circuit chip.
    Type: Grant
    Filed: October 12, 1999
    Date of Patent: October 16, 2001
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Hideyuki Unno, Manabu Itsumi, Shin-ichi Ohfuji, Masahiko Maeda
  • Publication number: 20010028115
    Abstract: In the present semiconductor device, a chip with an LSI circuit is secured to a board 3 (with the chip flipped) so as to be level. The LSI circuit on the chip is specified to operate normally only when the chip is level. Further, the back of the chip is processed so as to give stress to the chip. The chip has a reduced thickness of 50 &mgr;m or less (alternatively 30 &mgr;m to 50 &mgr;m). Therefore, when the chip is detached from the board, it deforms and is no longer level due to the stress, which prohibits the LSI circuit from operating normally. This way, the present semiconductor device ensures that no analysis can be conducted on the LSI circuit once the chip is detached.
    Type: Application
    Filed: March 30, 2001
    Publication date: October 11, 2001
    Inventors: Eiji Yanagawa, Akihiko Nakano, Toshinori Ohmi, Hironori Matsumoto, Tadao Takeda, Hideyuki Unno, Hiroshi Ban