Patents by Inventor Hien Pham

Hien Pham has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210350217
    Abstract: Numerous embodiments of analog neural memory arrays are disclosed. Certain embodiments contain improved mechanisms for pulling source lines down to ground expeditiously. This is useful, for example, to minimize the voltage drop for a read, program, or erase operation.
    Type: Application
    Filed: November 5, 2020
    Publication date: November 11, 2021
    Inventors: Hieu Van Tran, Thuan Vu, Stanley Hong, Stephen Trinh, Vipin Tiwari, Han Tran, Hien Pham
  • Publication number: 20210342682
    Abstract: Numerous embodiments of decoders for use with a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. The decoders include bit line decoders, word line decoders, control gate decoders, source line decoders, and erase gate decoders. In certain embodiments, a high voltage version and a low voltage version of a decoder is used.
    Type: Application
    Filed: July 6, 2021
    Publication date: November 4, 2021
    Inventors: Hieu Van Tran, STANLEY HONG, ANH LY, THUAN VU, HIEN PHAM, KHA NGUYEN, HAN TRAN
  • Patent number: 11120881
    Abstract: Numerous embodiments of an improved charge pump design are disclosed for generating the high voltages necessary to perform erase and program operations in non-volatile flash memory devices. In these embodiments, each boost stage in the charge pump is modified to overcome a deficiency in prior art charge pumps whereby voltage actually would decrease in the final boost stage. These modifications include the addition of one or more of a clock doubling circuit, a local self-precharge circuit, a feed-forward precharge circuit, a feed-backward precharge circuit, and a hybrid circuit comprising NMOS and PMOS transistors and diodes.
    Type: Grant
    Filed: October 20, 2020
    Date of Patent: September 14, 2021
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Anh Ly, Thuan Vu, Kha Nguyen, Hien Pham, Stanley Hong, Stephen T. Trinh
  • Patent number: 11087207
    Abstract: Numerous embodiments of decoders for use with a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. The decoders include bit line decoders, word line decoders, control gate decoders, source line decoders, and erase gate decoders. In certain embodiments, a high voltage version and a low voltage version of a decoder is used.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: August 10, 2021
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Stanley Hong, Anh Ly, Thuan Vu, Hien Pham, Kha Nguyen, Han Tran
  • Publication number: 20210118894
    Abstract: Numerous embodiments for reading or verifying a value stored in a selected memory cell in a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. In one embodiment, an input comprises a set of input bits that result in a series of input signals applied to a terminal of the selected memory cell, further resulting in a series of output signals that are digitized, shifted based on the bit location of the corresponding input bit in the set of input bits, and added to yield an output indicating a value stored in the selected memory cell.
    Type: Application
    Filed: December 23, 2020
    Publication date: April 22, 2021
    Inventors: Hieu Van Tran, Thuan Vu, Stephen Trinh, Stanley Hong, Toan Le, Nghia Le, Hien Pham
  • Publication number: 20210035643
    Abstract: Numerous embodiments of an improved charge pump design are disclosed for generating the high voltages necessary to perform erase and program operations in non-volatile flash memory devices. In these embodiments, each boost stage in the charge pump is modified to overcome a deficiency in prior art charge pumps whereby voltage actually would decrease in the final boost stage. These modifications include the addition of one or more of a clock doubling circuit, a local self-precharge circuit, a feed-forward precharge circuit, a feed-backward precharge circuit, and a hybrid circuit comprising NMOS and PMOS transistors and diodes.
    Type: Application
    Filed: October 20, 2020
    Publication date: February 4, 2021
    Inventors: Hieu Van Tran, Anh Ly, Thuan Vu, Kha Nguyen, Hien Pham, Stanley Hong, Stephen T. Trinh
  • Patent number: 10847227
    Abstract: Numerous embodiments of an improved charge pump design are disclosed for generating the high voltages necessary to perform erase and program operations in non-volatile flash memory devices. In these embodiments, each boost stage in the charge pump is modified to overcome a deficiency in prior art charge pumps whereby voltage actually would decrease in the final boost stage. These modifications include the addition of one or more of a clock doubling circuit, a local self-precharge circuit, a feed-forward precharge circuit, a feed-backward precharge circuit, and a hybrid circuit comprising NMOS and PMOS transistors and diodes.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: November 24, 2020
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Hieu Van Tran, Anh Ly, Thuan Vu, Kha Nguyen, Hien Pham, Stanley Hong, Stephen T. Trinh
  • Publication number: 20200342938
    Abstract: Various embodiments of word line decoders, control gate decoders, bit line decoders, low voltage row decoders, and high voltage row decoders and various types of physical layout designs for non-volatile flash memory arrays in an analog neural system are disclosed. Shared and segmented embodiments of high voltage row decoders are disclosed.
    Type: Application
    Filed: July 3, 2019
    Publication date: October 29, 2020
    Inventors: HIEU VAN TRAN, THUAN VU, STANLEY HONG, STEPHEN TRINH, ANH LY, HAN TRAN, KHA NGUYEN, HIEN PHAM
  • Publication number: 20200341951
    Abstract: The invention relates to a method for a model-driven extraction of event data representing an event occurring on a blockchain network by a computational device with access to the blockchain network. The computational device is configured as an ETL-device for executing an ETL-code to modify a data content of an external data structure external of the blockchain network using the extracted event data. The method comprising detecting the event, determining an event schema, providing and executing a the ETL-code. The ETL-code comprises machine-executable instructions for extracting the event data representing the detected event, transforming the extracted event data using the event schema to comply with a data model defining a logical structure of the external data structure and loading the transformed data to the external data structure to modify the data content of the external data structure.
    Type: Application
    Filed: March 25, 2020
    Publication date: October 29, 2020
    Inventors: Martin Oberhofer, Florian Mentzel, Hien Pham The, Thishanth Thevarajah
  • Publication number: 20200118632
    Abstract: Numerous embodiments of an improved charge pump design are disclosed for generating the high voltages necessary to perform erase and program operations in non-volatile flash memory devices. In these embodiments, each boost stage in the charge pump is modified to overcome a deficiency in prior art charge pumps whereby voltage actually would decrease in the final boost stage. These modifications include the addition of one or more of a clock doubling circuit, a local self-precharge circuit, a feed-forward precharge circuit, a feed-backward precharge circuit, and a hybrid circuit comprising NMOS and PMOS transistors and diodes.
    Type: Application
    Filed: December 13, 2018
    Publication date: April 16, 2020
    Inventors: HIEU VAN TRAN, ANH LY, THUAN VU, KHA NGUYEN, HIEN PHAM, STANLEY HONG, STEPHEN T. TRINH
  • Publication number: 20200019849
    Abstract: Numerous embodiments are disclosed for accessing redundant non-volatile memory cells in place of one or more rows or columns containing one or more faulty non-volatile memory cells during a program, erase, read, or neural read operation in an analog neural memory system used in a deep learning artificial neural network.
    Type: Application
    Filed: October 3, 2018
    Publication date: January 16, 2020
    Inventors: Hieu Van Tran, Stanley Hong, Thuan Vu, Anh Ly, Hien Pham, Kha Nguyen, Han Tran
  • Publication number: 20190286976
    Abstract: Numerous embodiments of decoders for use with a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. The decoders include bit line decoders, word line decoders, control gate decoders, source line decoders, and erase gate decoders. In certain embodiments, a high voltage version and a low voltage version of a decoder is used.
    Type: Application
    Filed: May 29, 2018
    Publication date: September 19, 2019
    Inventors: Hieu Van Tran, Stanley Hong, Anh Ly, Thuan Vu, Hien Pham, Kha Nguyen, Han TRan
  • Publication number: 20190205729
    Abstract: Numerous embodiments for processing the current output of a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. The embodiments comprise a summer circuit and an activation function circuit. The summer circuit and/or the activation function circuit comprise circuit elements that can be adjusted in response to the total possible current received from the VMM to optimize power consumption.
    Type: Application
    Filed: March 27, 2018
    Publication date: July 4, 2019
    Inventors: Hieu Van Tran, Stanley Hong, Anh Ly, Thuan Vu, Hien Pham, Kha Nguyen, Han Tran
  • Patent number: 10289803
    Abstract: Disclosed is a patient case identity determination method for a digital pathology system, which is performed by a patient case identity determination unit. The patient case identity determination method includes acquiring a digital slide image from a scanner; requesting a laboratory information system (LIS) to send patient/case information including a preprocessing step image that is obtained in a digital slide preprocessing step associated with the digital slide image; receiving the patient/case information including the preprocessing step image from the LIS; comparatively analyzing a pattern of the digital slide image and the preprocessing step image to calculate a synchronization rate and stores the calculated synchronization rate; and providing information about whether the digital slide image is identical to the patient/case information based on the calculated synchronization rate when a client application provides a reading of the digital slide image.
    Type: Grant
    Filed: July 22, 2016
    Date of Patent: May 14, 2019
    Assignee: INFINITT HEALTHCARE CO., LTD.
    Inventors: Man Won Hwang, Sung Yong Kim, Duy Hien Pham, Myung Jin Kim
  • Patent number: 9972086
    Abstract: Disclosed is an image quality evaluation method for a digital pathology system according to the present invention. The image quality evaluation method includes receiving a digital slide image by an image quality evaluation unit; dividing the digital slide image into a plurality of blocks by the image quality evaluation unit; analyzing the plurality of blocks to extract a foreground; calculating a blur for the extracted foreground; calculating brightness distortion for the extracted foreground; calculating contrast distortion for the extracted foreground; and evaluating the overall quality of the digital slide image using the blur, the brightness distortion, and the contrast distortion by the image quality evaluation unit.
    Type: Grant
    Filed: July 22, 2016
    Date of Patent: May 15, 2018
    Inventor: Duy Hien Pham
  • Publication number: 20180018426
    Abstract: Disclosed is a patient case identity determination method for a digital pathology system, which is performed by a patient case identity determination unit. The patient case identity determination method includes acquiring a digital slide image from a scanner; requesting a laboratory information system (LIS) to send patient/case information including a preprocessing step image that is obtained in a digital slide preprocessing step associated with the digital slide image; receiving the patient/case information including the preprocessing step image from the LIS; comparatively analyzing a pattern of the digital slide image and the preprocessing step image to calculate a synchronization rate and stores the calculated synchronization rate; and providing information about whether the digital slide image is identical to the patient/case information based on the calculated synchronization rate when a client application provides a reading of the digital slide image.
    Type: Application
    Filed: July 22, 2016
    Publication date: January 18, 2018
    Inventors: Man Won HWANG, Sung Yong KIM, Duy Hien PHAM, Myung Jin KIM
  • Publication number: 20180012352
    Abstract: Disclosed is an image quality evaluation method for a digital pathology system according to the present invention. The image quality evaluation method includes receiving a digital slide image by an image quality evaluation unit; dividing the digital slide image into a plurality of blocks by the image quality evaluation unit; analyzing the plurality of blocks to extract a foreground; calculating a blur for the extracted foreground; calculating brightness distortion for the extracted foreground; calculating contrast distortion for the extracted foreground; and evaluating the overall quality of the digital slide image using the blur, the brightness distortion, and the contrast distortion by the image quality evaluation unit.
    Type: Application
    Filed: July 22, 2016
    Publication date: January 11, 2018
    Inventor: Duy Hien PHAM
  • Patent number: 9036151
    Abstract: An optical parameter measuring apparatus for measuring optical parameters of an object includes a light source, a polarizing module, a Stokes polarimeter and a calculating module. The light source emits a light which is polarized by the polarizing module and received by the Stokes polarimeter. According to the light information generated by the Stokes polarimeter, Mueller matrixes of linear birefringence, circular birefringence, linear dichroism, circular dichroism and linear/circular depolarization of the object, and Stokes vector established according to the Mueller matrixes, the calculating module calculates the optical parameters.
    Type: Grant
    Filed: December 28, 2011
    Date of Patent: May 19, 2015
    Assignee: National Cheng Kung University
    Inventors: Yu-Lung Lo, Thi-Thu-Hien Pham
  • Publication number: 20150133291
    Abstract: Catalyst support materials that are coated with a thin carbon over-layer and methods for making the same are shown and described. In general, a supporting oxide material, which may or may not have a catalytic material already deposited on the surface, is coated with a thin carbon layer.
    Type: Application
    Filed: March 15, 2013
    Publication date: May 14, 2015
    Applicant: STC.UNM
    Inventors: Abhaya Datye, Hien Pham
  • Publication number: 20140077600
    Abstract: Embodiments relate to a system for controlling the storage and distribution of energy on a drill rig. The system includes a drill rig having a power consuming device, a power source for providing electrical power, a power storage device, and an electrical power bus. The power bus is electrically connected to the power source, the power consuming device, and the power storage device and is configured to provide an electrical pathway between one or more of the power source, power consuming device, and power storage device.
    Type: Application
    Filed: September 14, 2012
    Publication date: March 20, 2014
    Inventors: Robert Douglas CRYER, Ajith Kuttannair Kumar, Hien Pham, Ramesh K. Krishnan