Abstract: The determination of a plurality of sequences of words from a speech signal with a decreasing probability of correspondence utilizes the best word sequence as a basis and as further word sequences there are determined only those which enclose a part of the best word sequence, that is to say the remainder of these word sequences. To this end, the recognition involves first the formation of a word graph and the best word sequence is separately stored as a tree which initially has one branch only. The word boundaries of this word sequence form nodes in this tree. Because only nodes of this tree have to be taken into account for the next-best word sequences, the calculation is substantially simpler than if the complete word graph were first completely expanded in the form of a tree and completely searched again for each new word sequence.

Abstract: When a language model is to be used for the recognition of a speech signal and the vocabulary is composed as a tree, the language model value cannot be taken into account before the word end. Customarily, after each word end the comparison with a tree root is started anew, be it with a score which has been increased by the language model value so that the threshold value for the scores at which hypotheses are terminated must be high and hence many, even unattractive hypotheses remain active for a prolonged period of time. In order to avoid this, in accordance with the invention a correction value is added to the score for at least a part of the nodes of the vocabulary tree; the sum of the correction values on the path to a word then may not be greater than the language model value for the relevant word. As a result, for each test signal the scores of all hypotheses are of a comparable order of magnitude.

Abstract: A tag hit enable method for low power cache operation is provided which comprises inactivating all output buffers during all cache operations generating a tag hit enable signal, enabling/disabling dataram output buffers with said tag signal, activating only said output buffers receiving a hit state from a tag ram in order to transfer data from dataram to a CPU data bus, pre-charging said tag hit signals to tag miss signals, and disabling all data output buffers with said tag miss signals.

Abstract: A method for invalidating a line in a cache block in a cache memory during a cache write operation, wherein the cache block includes two or more lines of data sharing a common tag address. The method involves generating a read miss request with respect to one or more lines in the cache block, including a tag and block address and an invalidation control bit. When the invalidation control bit is on, the invalidation control bit causes the setting of the validity bits, for those lines in the cache block other than the one or more lines for which the read miss request is generated, to invalid. When the invalidation control bit is off, the invalidation control bit prevents the resetting of the validity bits, for those lines in the cache block other than the one or more lines for which the read miss request is generated.

Abstract: A method for updating a LRU array in a cache having a RAM. The LRU array has a self-timing signal for the read operation of the LRU array, in conjunction with a cache RAM read cycle. According to the method, first, a cache RAM cycle is begun. Then, it is determined whether a hit condition exists with respect to a tag associated with the LRU array. A self-timing signal is generated if the hit condition exists. In response to the self-timing signal, and in the cache RAM read cycle, an LRU write operation is begun with respect to the LRU array. The LRU write operation includes the steps of providing a write signal to the LRU array, and of precharging the LRU array. The LRU write operation is extended for a time sufficient for the precharging of the LRU bit line to complete. This can result in the LRU write operation extending into the next cache cycle. Additionally, the LRU array may be provided with an LRU dummy cell.

Abstract: A method for avoiding a tag duplicate fault. The method includes the steps of using a master - slave tag; selecting a first tag as a master and a second tag as a slave; inhibiting the second tag from initiating a hit signal when the first tag is set for a hit condition, and enabling the second tag to initiate a bit signal when the first tag is set for a miss condition.