Abstract: A flash translation layer method, system, and computer program product, include performing a virtualization of a meta-flash translation layer by: instantiating a range in a NAND chip comprising the number of free blocks using a meta-FTL to create a compatible range of blocks for a type of a feature and a flash characteristic of a translation table if a number of free blocks are available in the NAND chip and instantiating a second range in the NAND chip comprising a second number of free blocks using the meta-FTL to create a second compatible range of blocks for a second type of feature and a second flash characteristic of the translation table, and dynamically programming data on the fly based on an input requirement of a request into the range and the second range.

Abstract: Examples of techniques for an integrated wafer-level processing system are disclosed. In one example implementation according to aspects of the present disclosure, an integrated wafer-level processing system includes a memory wafer and a processing element connected to the memory wafer via a data connection.

Abstract: A flash translation layer method, system, and computer program product, include performing a virtualization of a meta-flash translation layer by: instantiating a range in a NAND chip comprising the number of free blocks using a meta-FTL to create a compatible range of blocks for a type of a feature and a flash characteristic of a translation table if a number of free blocks are available in the NAND chip and instantiating a second range in the NAND chip comprising a second number of free blocks using the meta-FTL to create a second compatible range of blocks for a second type of feature and a second flash characteristic of the translation table, and dynamically programming data on the fly based on an input requirement of a request into the range and the second range.

Abstract: A flash translation layer method, system, and computer program product, include sending a request with a type of feature and a flash characteristic of a translation table for a Solid-State disk, receiving, via a meta-flash translation layer (meta-FTL), the request and checking for a number of free blocks in a NAND chip, and instantiating a range in the NAND chip including the number of free blocks using the meta-FTL to create a compatible range of blocks for the type of feature and the flash characteristic of the translation table if the checking returns a confirmation that the number of free blocks is available.

Abstract: Examples of techniques for an integrated wafer-level processing system are disclosed. In one example implementation according to aspects of the present disclosure, an integrated wafer-level processing system includes a memory wafer and a processing element connected to the memory wafer via a data connection.

Abstract: Examples of techniques for an integrated wafer-level processing system are disclosed. In one example implementation according to aspects of the present disclosure, an integrated wafer-level processing system includes a memory wafer and a processing element connected to the memory wafer via a data connection.

Abstract: Examples of techniques for a built-in self-test (BIST) for embedded spin-transfer torque magnetic random access memory (STT-MRAM) are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include: initiating, by a processor, a BIST for the STT-MRAM; performing, by the processor, an error-correcting code (ECC) test for a portion of the STT-MRAM; responsive to the ECC test not being passed, determining whether a maximum signal is reached; responsive to the maximum signal not being reached, increasing the signal and performing the ECC test again; and responsive to the maximum signal being reached, determining that the portion of the STT-MRAM is bad.

Abstract: Techniques for improving the security of nonvolatile memory such as magnetic random access memory (MRAM) are provided. In one aspect, a method of operating a nonvolatile memory chip is provided. The method includes: overwriting data stored on the nonvolatile memory chip automatically upon the nonvolatile memory chip being powered on. For example, all bits in the nonvolatile memory chip can be written to either i) a predetermined data state (e.g., a logic 1 or a logic 0) or ii) a random data state. A system is also provided that includes: a nonvolatile memory chip; and a writing circuit configured to overwrite data stored on the nonvolatile memory chip automatically upon the nonvolatile memory chip being powered on.

Abstract: Techniques for improving the security of nonvolatile memory such as magnetic random access memory (MRAM) are provided. In one aspect, a method of operating a nonvolatile memory chip is provided. The method includes: overwriting data stored on the nonvolatile memory chip automatically upon the nonvolatile memory chip being powered on. For example, all bits in the nonvolatile memory chip can be written to either i) a predetermined data state (e.g., a logic 1 or a logic 0) or ii) a random data state. A system is also provided that includes: a nonvolatile memory chip; and a writing circuit configured to overwrite data stored on the nonvolatile memory chip automatically upon the nonvolatile memory chip being powered on.

Abstract: A method, system and memory controller for implementing memory hierarchy placement decisions in a memory system including direct routing of arriving data into a main memory system and selective injection of the data or computed results into a processor cache in a computer system. A memory controller, or a processing element in a memory system, selectively drives placement of data into other levels of the memory hierarchy. The decision to inject into the hierarchy can be triggered by the arrival of data from an input output (IO) device, from computation, or from a directive of an in-memory processing element.

Abstract: An aspect includes determining a configuration change to at least one memory device of a memory system. A band switch enable command is sent from a memory controller to the at least one memory device indicating the configuration change. One or more internal circuits of the at least one memory device are set into a quiescent mode based on receiving the band enable command. One or more of a voltage and a frequency of the at least one memory device are adjusted to implement the configuration change. A band switch disable command is sent from the memory controller to the at least one memory device based on completing the adjusting. The one or more internal circuits are enabled to operate using the adjustment based on receiving the band switch disable command from the memory controller.

Abstract: A memory management system and a method of managing a memory device are described. The system includes a memory device with a memory array to store data and associated error correction coding (ECC) bits and an extended correction table. The extended correction table stores error information additional to the ECC bits for one or more of the data in the memory array. The system also includes a controller to control the memory device to write and read the data.

Abstract: A memory management system and a method of managing a memory device are described. The system includes a memory device with a memory array to store data and associated error correction coding (ECC) bits and an extended correction table. The extended correction table stores error information additional to the ECC bits for one or more of the data in the memory array. The system also includes a controller to control the memory device to write and read the data.

Abstract: Embodiments of the present disclosure provide an approach for monitoring the health and predicting the failure of dynamic random-access memory (DRAM) devices with embedded error-correcting code (ECC). Additional registers are embedded on the DRAM device to store information about the DRAM, such as the number and location of soft errors detected by the device. When the DRAM device detects a soft error, it will update the information stored in the additional registers. A controller compares the information stored in the additional registers to associated thresholds. In some embodiments, after comparing the information to the associated thresholds, the controller may determine whether to schedule a repair action. In other embodiments, the controller may determine whether to alert the memory controller that the DRAM may be failing.

Abstract: Examples of techniques for a built-in self-test (BIST) for embedded spin-transfer torque magnetic random access memory (STT-MRAM) are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include: initiating, by a processor, a BIST for the STT-MRAM; performing, by the processor, an error-correcting code (ECC) test for a portion of the STT-MRAM; responsive to the ECC test not being passed, determining whether a maximum signal is reached; responsive to the maximum signal not being reached, increasing the signal and performing the ECC test again; and responsive to the maximum signal being reached, determining that the portion of the STT-MRAM is bad.

Abstract: Embodiments of the present disclosure provide a method, computer program product, and system for monitoring a dynamic random-access memory (DRAM) device to detect and respond to a cryogenic attack. A processor receives a set of memory information about a DRAM device. The processor then determines a set of error indicators by processing the memory information using a set of decision parameters. The error indicators are then compared to an attack syndrome to determine if the DRAM is experiencing a cryogenic attack. If the DRAM is experiencing a cryogenic attack, access to the DRAM device is disabled.

Abstract: A method, system and memory controller for implementing memory hierarchy placement decisions in a memory system including direct routing of arriving data into a main memory system and selective injection of the data or computed results into a processor cache in a computer system. A memory controller, or a processing element in a memory system, selectively drives placement of data into other levels of the memory hierarchy. The decision to inject into the hierarchy can be triggered by the arrival of data from an input output (IO) device, from computation, or from a directive of an in-memory processing element.

Abstract: An aspect includes determining a configuration change to at least one memory device of a memory system. A band switch enable command is sent from a memory controller to the at least one memory device indicating the configuration change. One or more internal circuits of the at least one memory device are set into a quiescent mode based on receiving the band enable command. One or more of a voltage and a frequency of the at least one memory device are adjusted to implement the configuration change. A band switch disable command is sent from the memory controller to the at least one memory device based on completing the adjusting. The one or more internal circuits are enabled to operate using the adjustment based on receiving the band switch disable command from the memory controller.

Abstract: According to one aspect, a method for adaptive error correction in a memory system includes reading data from a memory array of a non-volatile memory device in the memory system. Error correcting logic checks the data for at least one error condition stored in the memory array. Based on determining that the at least one error condition exists, a write-back indicator is asserted by the error correcting logic to request correction of the at least one error condition, where the write-back indicator is a discrete signal sent to a memory controller, and the at least one non-volatile memory device asserting the write-back indicator extends cycle timing monitored by the memory controller while the write-back indicator is asserted. Based on determining that the at least one error condition does not exist, accesses of the memory array continue without asserting the write-back indicator.

Abstract: A method, system and memory controller for implementing memory hierarchy placement decisions in a memory system including direct routing of arriving data into a main memory system and selective injection of the data or computed results into a processor cache in a computer system. A memory controller, or a processing element in a memory system, selectively drives placement of data into other levels of the memory hierarchy. The decision to inject into the hierarchy can be triggered by the arrival of data from an input output (IO) device, from computation, or from a directive of an in-memory processing element.