Abstract: The present invention encompasses monoclonal and chimeric antibodies that bind to lipoteichoic acid of Gram positive bacteria. The antibodies also bind to whole bacteria and enhance phagocytosis and killing of the bacteria in vitro and enhance protection from lethal infection in vivo. The mouse monoclonal antibody has been humanized and the resulting chimeric antibody provides a previously unknown means to diagnose, prevent and/or treat infections caused by gram positive bacteria bearing lipoteichoic acid. This invention also encompasses a peptide mimic of the lipoteichoic acid epitope binding site defined by the monoclonal antibody. This epitope or epitope peptide mimic identifies other antibodies that may bind to the lipoteichoic acid epitope. Moreover, the epitope or epitope peptide mimic provides a valuable substrate for the generation of vaccines or other therapeutics.

Abstract: A memory architecture is disclosed that employs multiple column redundancies which provide multiple options for replacing a defective global odd or even bit line. Each column memory has two multiplexers, one for selecting a global odd bit line and another for selecting a global even bit line. Two or more column redundancies are coupled to each of the multiplexer in the column memory. In a first embodiment, the global odd and even bit lines are connected through odd and even sense amps in a regular column. In a second embodiment, the global odd bit line in a regular column connects through odd sense amps, while the global even bit line in the regular column connects through even sense amps. In a third embodiment, two or more sets of redundancy columns are commonly coupled to a left adjacent regular column and a right adjacent regular column.

Abstract: The invention discloses a low-power ternary CAM by utilizing four encoded comparand datalines, C0, C1, C2, and C3 in a twin ternary cell. The twin ternary cell is a composite of two ternary CAM bits. The two binary CAM bits are coded so that only one of four comparand datalines is toggled during a compare operation. The encoded data is stored and used for comparison. In one embodiment, the four possible states for the 2 bit comparands are coded as 0001, 0010, 0100, and 1000.

Abstract: The present invention discloses a parallel test circuit and method for testing even bit line and odd bit line in a memory block simultaneously. The parallel test circuit comprises an even test circuit for testing an even bit line and an odd test circuit for testing an odd bit line. The parallel test circuit also includes a write circuit for writing data to a bit line, a read circuit including a data sense amp, an output buffer, and a comparator. Furthermore, the present invention provides the capability to conduct disturbance test in neighboring even and odd cells.

Abstract: A negative wordline DRAM array having n groups of m wordlines, in which one group is driven by a group decoder circuit (having a voltage swing between ground and a circuit high voltage (2 v)) and one driver circuit in each group is exposed to a boosted wordline high voltage (2.8 v) greater than the circuit high voltage, in which the wordline driver circuits have an output stage comprising a standard nfet in series with a high threshold voltage pfet, so that, during activation, the unselected driver circuits exposed to the boosted wordline high voltage have a very low leakage through the pfet, while the selected driver circuit has a high but tolerable leakage (2 &mgr;A) because Vqs on the nfet is nearly at the nfet threshold.

Abstract: Provision of differential etching of layers by, for example, an etch stop layer or implantation, allows a second trough etch to be performed in accordance with a block-out mask (which does not require high accuracy of registration) to provide troughs or recesses of different depths in layers of insulator. When the recesses or troughs are filled by metal deposition and patterned by planarization in accordance with damascene processing, structurally robust conductors of differing thicknesses may be achieved and optimized to enhance noise immunity and/or signal propagation speed in different functional regions of an integrated circuit such as the so-called array and support portions of a dynamic random access memory.

Abstract: DRAM with column slices improves circuit redundancy. Slices have global column length, and memory is divided in groups with size of redundancy columns having slices. Failure detected among slices of corresponding storage is replaced by corresponding redundancy column slice, such that column redundancy division is in vertical column direction. Column includes global data line shared by column slices and multiple blocks. Redundant column is added to memory array, and redundant control circuits or comparator are proximate to data sense amplifiers. Defective column address are provided to controller through non-volatile memory, or laser-blown or electrically-programmable fuses. When column address is presented, incoming address is compared with stored address, such that select data is output on redundant data line when equal addresses (i.e., hit detect), or normal data is output when unequal addresses (i.e., "miss" detected).

Abstract: Disclosed is a semiconductor memory having a hierarchical bit line and/or word line architecture. In one embodiment, a memory having a hierarchical bit line architecture, particularly suitable for cells smaller than 8F.sup.2, includes a master bit line pair in each column, including first and second master bit lines with portions vertically spaced from one another. The first and second master bit lines twist with respect to one another in the vertical direction such that the first master bit line alternately overlies and underlies the second master bit line. A plurality of local bit line pairs in each column are coupled to memory cells, with at least one of the local bit lines coupled to a master bit line. In other embodiments, hierarchical word line configurations are disclosed including master word lines, sub-master word lines, and local word lines, electrically interconnected to one another via either switches, electrical contacts, or electrical circuits.

Abstract: A method and apparatus for repairing a semiconductor memory device. A row redundancy replacement arrangement is provided to repair the memory device consisting of a first plurality of redundant true word lines and a second plurality of redundant complement word lines to simultaneously replace the same first number of first normal word lines and the same second number of the normal complement word lines. An address reordering scheme, preferably implemented as a word line selector circuit and controlled by redundancy control logic and address inputs, allows the redundant true (complement) word lines to replace the normal true (complement) word lines when making the repair. The redundancy replacement arrangement ensures that consistency of the bit map is maintained at all times, irrespective whether the memory device operates in a normal or in a redundancy mode. This approach introduces an added flexibility of incorporating the redundancy replacement without affecting the column access speed.

Abstract: A modular, threaded container for growing plants and subsequently increasing size of the container. Modules are arranged to be stacked on one another to increase overall height of the modular assembly. Individual modules include a top module having bottom threading only, intermediate modules open at the top and bottom and having top and bottom threading, and a bottom module having a floor and threading at the top only. The container may optionally include frustoconical modules, a first frustoconical bottom module configured to replace an open intermediate module with a module closed at the bottom, and a second frustoconical module closed at the bottom of dimensions and configuration different from those of the first bottom module. The plant is grown in a container having relatively few modules. After growth has occurred, the bottom module is removed and an intermediate module open at both ends is filled with growing medium and is inserted in series prior to replacing the bottom module.

Abstract: A circuit and method of using a test mode to control the timing of an internal signal using an external control in an integrated circuit. The test mode is designed such that the timing of the internal signal is derived from the external control which can be arbitrarily controlled by a tester. The external signal can be applied to an existing pin for chip control, provided that there is no conflict between the test mode and the operation of the integrated circuit.

Abstract: A method for generating a floating bitline test mode using digitally controllable bitline equalizers is provided. The method utilizes digitally controlled dummy timing cycles to detect a leaky bitline during the floating bitline test mode. A negative pulsed TEST signal is generated to cause the bitline equalizers to go low and cause the floating bitline state. The implementation of dummy timing cycles eliminates the need for additional external control of internal timings during a bitline test mode. Upon the termination of the dummy timing cycle, the normal read operation continues without interruption.

Abstract: A semiconductor structure having electrical conductors positioned over each other, but electrically isolated from each other, is disclosed. The lower conductor has a recess in its upper surface, and the recess is at least partially filled with an oxide-type material, thereby isolating the lower conductor from the upper conductor. These conductors would normally contact each other because of the somewhat imprecise patterning and etching steps used to fabricate a multitude of conductive elements, e.g., in a very dense semiconductor structure. Stacked capacitor cells incorporating this structure are also disclosed.

Abstract: Improved gas exhaust apparatus of a semiconductor plant for substantially reducing the accumulation of solid substance on the surface of a gas exhaust system is disclosed. The apparatus includes a heating section for providing a thermal chamber, thereby transforming incoming gas and oxygen into solid substance. A barrier section is secured to an inner surface of the heating section for preventing the solid substance from accumulating on the inner surface of the heating section. A scrubbing section attached to the heating section is used to expel the solid substance out of the gas exhaust apparatus.

Abstract: A circuit and method of using a test mode to control the timing of an internal signal using an external control in an integrated circuit. The test mode is designed such that the timing of the internal signal is derived from the external control which can be arbitrarily controlled by a tester. The external signal can be applied to an existing pin for chip control, provided that there is no conflict between the test mode and the operation of the integrated circuit.

Abstract: A semiconductor structure to prevent gate wrap-around and corner parasitic leakage comprising a semiconductor substrate having a planar surface. A trench is located in the substrate, the trench having a sidewall. An intersection of the trench and the surface forms a corner. A dielectric lines the sidewall of the trench. And, a corner dielectric co-aligned with the corner extends a subminimum dimension distance over the substrate from the corner.

Abstract: Row redundancy control circuits which effectively reduce design space are arranged parallel to word direction and are arranged at the bottom of the redundancy block. This architecture change makes it possible to effectively lay out the redundancy control block by introducing (1) split-global-bus shared with local row redundancy wires, (2) half-length-one-way row redundancy-wordline-enable-signal wires which allows space saving, and (3) distributed wordline enable decoders designed to take advantage of the saved space. An illegal normal/redundancy access problem caused by the address versus timing skew has also been solved. The timing necessary for this detection is given locally by using its adjacent redundancy match detection. This allows the circuit to operate completely as an address driven circuit, resulting in fast and reliable redundancy match detection. In addition, a sample wordline enable signal (SWLE) is generated by using row redundancy match detection.

Abstract: A method of testing a RAM. The RAM array is arranged in rows and columns. The rows are grouped into word line groups. The method includes the steps of: a) asserting an array select signal; b) selecting a group of rows in the array; c) selecting at least one row of the selected group of rows; and, d) repeating steps b and c until all of the groups are selected. Array Sense Amps may be set when the first group is selected and remain set until the last group is selected. In one test, word lines in all of the selected rows are activated and remain activated until the final selected row is selected. In a second test, word lines in selected groups are toggled with RAS. If a group contains a known defective word line, that group is either not addressed or its selection is disabled. In each selected group, one row, alternating rows or, all of the rows may be selected.

Abstract: A latched row decoder for a Random Access Memory (RAM). The Decoder includes a set-reset latch that is set when addressed and remains set until reset by a PRE signal; address select logic; a reset device; and gated word line drives. The latch, when set, enables four word line drivers that are driven individually depending on two row address bits. During test, latched decoders may be selected sequentially and not reset, leaving drivers enabled until a test is complete. Thus some or all word lines may be driven simultaneously during test. A RAM including the latched decoder of the present invention has a normal random access mode and at least 4 test modes. The test modes are: Long t.sub.RAS word line disturb mode; toggled word line disturb mode; transfer gate stress mode; and a stress test mode.

Abstract: In the Preferred embodiment of the present invention, a bit line pair is coupled through a pair of high-resistance pass gates to a sense amp. During sense, the high-resistance pass gates act in conjunction with the charge stored on the bit line pair as, effectively, a high-resistance passive load for the sense amp. A control circuit selectively switches on and off bit line equalization coincident with selectively passing either the equalization voltage or set voltages to the sense amp and an active sense amp load. Further, after it is set, the sense amp is selectively connected to LDLs through low-resistance column select pass gates. Therefore, the sense amp quickly discharges one of the connected LDL pair while the bit line voltage remains essentially unchanged. Thus, data is passed from the sense amp to a second sense amplifier and off chip. After data is passed to the LDLs, the control circuit enables the active sense amp load to pull the sense amp high side to a full up level.