Patents by Inventor Hing Wong

Hing Wong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5610867
    Abstract: In the Preferred embodiment of the present invention, a bit line pair is coupled through a pair of high-resistance pass gates to a sense amp. During sense, the high-resistance pass gates act in conjunction with the charge stored on the bit line pair as, effectively, a high-resistance passive load for the sense amp. A control circuit selectively switches on and off bit line equalization coincident with selectively passing either the equalization voltage or set voltages to the sense amp and an active sense amp load. Further, after it is set, the sense amp is selectively connected to LDLs through low-resistance column select pass gates. Therefore, the sense amp quickly discharges one of the connected LDL pair while the bit line voltage remains essentially unchanged. Thus, data is passed from the sense amp to a second sense amplifier and off chip. After data is passed to the LDLs, the control circuit enables the active sense amp load to pull the sense amp high side to a full up level.
    Type: Grant
    Filed: September 28, 1995
    Date of Patent: March 11, 1997
    Assignee: International Business Machines Corporation
    Inventors: John K. DeBrosse, Toshiaki Kirihata, Hing Wong
  • Patent number: 5602051
    Abstract: An improved method for isolating electrical conductors which are positioned over each other is disclosed. These conductors would normally contact each other because of the somewhat imprecise patterning and etching steps used to fabricate a multitude of conductive elements, e.g., in a very dense semiconductor structure. The method involves forming a recess in the upper surface of the lower conductor, and then at least partially filling the recess with an oxide-type material. This method is particularly valuable in the construction of stacked capacitor cells. Cells prepared using this technique also form part of this invention.
    Type: Grant
    Filed: October 6, 1995
    Date of Patent: February 11, 1997
    Assignee: International Business Machines Corporation
    Inventors: John E. Cronin, John K. DeBrosse, Hing Wong
  • Patent number: 5559050
    Abstract: An anomalous threshold voltage dependence on channel width measured on 0.25 .mu.m ground rule generation trench-isolated buried-channel p-MOSFETs is used to enhance circuit performance. As the channel width is reduced, the magnitude of the threshold voltage first decreases before the onset of the expected sharp rise in V.sub.t for widths narrower than 0.4 .mu.m. Modeling shows that a "boron puddle" is created near the trench bounded edge as a result of transient enhanced diffusion (TED) during the gate oxidation step, which imposes a penalty on the off-current of narrow devices. TED is governed by interstitials produced by a deep phosphorus implant, used for latchup suppression, diffusing towards the trench sidewall and top surface of the device.
    Type: Grant
    Filed: June 30, 1994
    Date of Patent: September 24, 1996
    Assignee: International Business Machines Corporation
    Inventors: Johann Alsmeier, Wayne F. Ellis, Jack A. Mandelman, Hing Wong
  • Patent number: 5559739
    Abstract: A Dynamic Random Access Memory (DRAM) including an array of memory cells arranged in rows and columns, a word line in each row responsive to a row address and, a pair of complementary bit lines in each column. The DRAM also includes a sense amp in each column connected between a sense enable and the pair of complementary bit lines. The sense amp is a pair of cross coupled NFETs, with the sources of the NFETs connected to the sense amp enable. A bit line pre-charge is connected to each pair of complementary bit lines. The bit line pre-charge is connected between the complementary bit line pair and a reference voltage. A test control circuit selectively holds the sense amp disabled and the bit line pairs in a pre-charge state in response to a test control signal. An active sense amp load connected between the sense amp and a load enable latches data in the sense amp. The active sense amp load is a pair of cross coupled PFETs connected to the sense amp with the sources of the PFETs connected to the load enable.
    Type: Grant
    Filed: September 28, 1995
    Date of Patent: September 24, 1996
    Assignee: International Business Machines Corporation
    Inventors: John K. DeBrosse, Toshiaki Kirihata, Hing Wong
  • Patent number: 5556802
    Abstract: A method for forming a capacitor on a substrate having a contact below a top layer including the steps of:Spinning on a layer of photoresist material. Exposing the photoresist to light to establish a standing wave pattern to fix prominences of photoresist separated by separation areas. Each prominence extends a prominence height from the top layer to a top. Developing the photoresist to fix an erose face on each prominence, each face extending from the top layer to the top. Depositing a first oxide intermediate prominences to effect accumulation of the first oxide to an oxide height at least equal to the prominence height. Etching the first oxide to expose each top. Dissolving the photoresist to uncover oxide mandrels. Each mandrel extends a mandrel height from the top layer to a mandrel top; each mandrel has an erose mandrel face intermediate the top layer and the mandrel top. Etching the top layer to expose the contact.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: September 17, 1996
    Assignee: International Business Machines Corporation
    Inventors: Paul E. Bakeman, Jr., Bomy A. Chen, John E. Cronin, Steven J. Holmes, Hing Wong
  • Patent number: 5521422
    Abstract: A semiconductor structure to prevent gate wrap-around and corner parasitic leakage comprising a semiconductor substrate having a planar surface. A trench is located in the substrate, the trench having a sidewall. An intersection of the trench and the surface forms a corner. A dielectric lines the sidewall of the trench. And, a corner dielectric co-aligned with the corner extends a subminimum dimension distance over the substrate from the corner.
    Type: Grant
    Filed: December 2, 1994
    Date of Patent: May 28, 1996
    Assignee: International Business Machines Corporation
    Inventors: Jack A. Mandelman, Brian J. Machesney, Hing Wong, Michael D. Armacost, Pai-Hung Pan
  • Patent number: 5517442
    Abstract: The present invention is a bus arrangement for a wide I/O Random Access Memory (RAM). The bus arrangement includes a global address bus which drives row/column predecoders and redundancy comparators placed at each edge of the memory array. Two banks of sixteen data I/O (DQs), one bank for each half chip, are placed at either end of the chip providing up to a .times.32 I/O organization. The main Read/Write Data lines (RWD) are more densely populated near the chip edge than the chip center to provide .times.4 and .times.8 options, as well. A local address bus is in the open space between the RWDs to redrive the global address lines at their quarter points.
    Type: Grant
    Filed: March 13, 1995
    Date of Patent: May 14, 1996
    Assignee: International Business Machines Corporation
    Inventors: Toshiaki Kirihata, Yohji Watanabe, Hing Wong
  • Patent number: 5276641
    Abstract: A hybrid open/folded bit line sense amplifier arrangement and accompanying circuitry primarily for use on a ULSI DRAM memory chip to reduce the area needed for a memory cell and eliminate noise between bit lines. The circuitry includes two memory arrays containing a plurality of memory cells interconnected by a plurality of bit lines and word lines. In the preferred embodiment, the memory cells are accessible on every two out of three bit lines encountered by a word line. A set of open bit line sense amplifiers each with two connectors, one multiplexed to a number of bit lines in the first array and the other multiplexed to a number of bit lines in the second array is provided. Each memory array has a set of folded bit line sense amplifiers with two connectors each connector multiplexed to a number of bit lines in the array. The control circuitry with multiplexing ensures that the connectors of the sense amplifiers access only one bit lines at a time.
    Type: Grant
    Filed: December 12, 1991
    Date of Patent: January 4, 1994
    Assignee: International Business Machines Corporation
    Inventors: Edmund J. Sprogis, Hing Wong
  • Patent number: 5268274
    Abstract: Nucleic acid sequences encoding the bacterial cellulose synthase operon derived from Acetobacter are disclosed. Methods for isolating the genes, vectors containing the genes, and transformed hosts useful for the expression of recombinant bacterial cellulose synthase or production of cellulose are also described.
    Type: Grant
    Filed: April 22, 1991
    Date of Patent: December 7, 1993
    Assignee: Cetus Corporation
    Inventors: Arie Ben-Bassat, Roger D. Calhoon, Anna L. Fear, David H. Gelfand, James H. Meade, Rony Tal, Hing Wong, Moshe Benziman