Abstract: Some examples described herein relate to a design system and a method for printed circuit board (PCB) design. In an example, a design system includes a processor and a memory coupled to the processor. The memory stores instruction code. The processor is configured to execute the instruction code to provide a workspace in a user interface in which a PCB design comprising multiple layers is capable of being created; provide a list of layout templates in the user interface; and provide an insert function, via the user interface, configured to insert a selected layout template of the list of layout templates into the workspace to be included in the PCB design. Each layout template of the list of layout templates is a tile layout that includes a layout component and metal lines that extend to one or more edges of the tile layout.

Abstract: A technique includes providing transmitters that are each associated with a data bit line of a bus, and each transmitter is clocked by an associated transmit clock signal. The technique includes determining a baseline offset to apply to a base clock signal to synchronize the base clock signal to a source clock signal of a source that supplies data to the transmitters. For each transmitter, an associated phase offset is determined to compensate for an associated skew. The phase of each transmit clock signal is controlled based on the associated phase offset and the baseline offset.

Abstract: A method and device are disclosed. In one embodiment the method includes driving a first clock domain reference signal on a first clock tree and driving a second clock domain reference signal on a second clock tree. The first tree routes the first signal from a PLL to a first clock domain drop off circuit and the second tree routes the second signal from the PLL to a second clock domain drop off circuit. A jitter produced from the second tree is less than a jitter produced from the first tree. The method continues by detecting any phase misalignment between the first signal and the second signal. The method also causes the first signal to be delayed so that it aligns with the second signal.

Abstract: A method and device are disclosed. In one embodiment the method includes driving a first clock domain reference signal on a first clock tree and driving a second clock domain reference signal on a second clock tree. The first tree routes the first signal from a PLL to a first clock domain drop off circuit and the second tree routes the second signal from the PLL to a second clock domain drop off circuit. A jitter produced from the second tree is less than a jitter produced from the first tree. The method continues by detecting any phase misalignment between the first signal and the second signal. The method also causes the first signal to be delayed so that it aligns with the second signal.

Abstract: An embodiment of the present invention is a technique to calibrate an integrating receiver. A delay calibration circuit calibrates an adjusting code of a chain of delay elements and positioning of at least an integrating strobe used to define an integration window for the integrating receiver. An integrating receiver pulse generator generates an IR pulse from the at least integrating strobe. A calibration controller controls calibrating the adjusting code and the positioning of the at least integrating strobe.

Abstract: Operation of a video cassette player is facilitated by providing a VBI decoder which decodes information, such as title, channel, date, time and length of broadcast programs and utilizing the information in providing directory of the programs as well as control of the VCR. The video cassette player is also provided with a VBI encoder for inserting control as well as directory information into the tape, either in the VBI portions of the video track or in the control track.

Abstract: A method and system for a configurable Vcc reference and Vss reference differential current mode transmitter is described. The system includes a Vss reference differential current mode driver, a Vcc reference differential current mode driver coupled to the Vss reference current mode driver, and a controller circuit coupled to the Vss reference differential current mode driver and the Vcc reference differential current mode driver to select between the Vss reference differential current mode driver and the Vcc reference differential current mode driver based on a type of transmission interface.

Abstract: A technique includes providing transmitters that are each associated with a data bit line of a bus, and each transmitter is clocked by an associated transmit clock signal. The technique includes determining a baseline offset to apply to a base clock signal to synchronize the base clock signal to a source clock signal of a source that supplies data to the transmitters. For each transmitter, an associated phase offset is determined to compensate for an associated skew. The phase of each transmit clock signal is controlled based on the associated phase offset and the baseline offset.

Abstract: The invention includes a method to adjust integrated circuit device I/O bus timing. In one embodiment, the method includes comparing an alignment between an edge of a first clock signal to a center of a data packet to produce an alignment offset signal and adjusting the first clock signal using a variable delay device in response to the alignment offset signal to substantially align the edge of the first clock signal to the center of the data packet. Other embodiments are claimed and described.

Abstract: Methods and devices for calibrating a driver on a slave device, using a master device driver as a load, are disclosed. A master reference driver is integrated on the same circuit as the master device driver, with both drivers having the same layout and geometry. The master reference driver is calibrated using a selected load impedance that includes the nominal slave device driver impedance and any other impedance elements. The same calibrated driver setting is concurrently applied to both the master driver and the master reference driver, while the slave device drives the master driver. The voltage at the master driver is compared to the voltage at the master reference driver, and the slave device driver impedance is adjusted until those voltages match. The resulting calibration of the slave device driver impedance is largely independent of the actual impedance of the master device driver.

Abstract: A first device delivers a clock offset message to a second device. The second device offsets its data transmission according to the clock offset message. A test pattern is transmitted from the second device to the first device. The first device then checks the received test pattern to determine whether the transmission was successful. The first device can then deliver an additional clock offset message to the second device to instruct the second device to offset its data transmission by a different value than was used previously. The second device again transmits the test pattern and the first device again checks the received pattern. By trying a number of clock offset values and determining which values result in successful transmissions of data, the first device can determine the optimal clock offset value and instruct the second device to use this value for all transmissions.

Abstract: A system for interfacing over a multi-drop bus comprising a single-ended control interface coupled with a first power supply, and a common supply and a plurality of single-ended memory interfaces coupled with a second power supply, the common supply and coupled directly to the control interface. The control interface is configured to drive a control output signal and the memory interface is configured to drive a memory output signal. The output signals are driven to the common supply to transfer a logic low.

Abstract: A first device delivers a clock offset message to a second device. The second device offsets its data transmission according to the clock offset message. A test pattern is transmitted from the second device to the first device. The first device then checks the received test pattern to determine whether the transmission was successful. The first device can then deliver an additional clock offset message to the second device to instruct the second device to offset its data transmission by a different value than was used previously. The second device again transmits the test pattern and the first device again checks the received pattern. By trying a number of clock offset values and determining which values result in successful transmissions of data, the first device can determine the optimal clock offset value and instruct the second device to use this value for all transmissions.

Abstract: A method, system, and device capable of generating one or more clocks internally to detect, sample, and receive synchronous data streams and eliminate the need for corresponding external synchronization clocks for each data stream. One aspect of the clock generator provides a two-stage interpolation system. In a first stage, two clocks are selected which accurately detect a calibration data sample. In a second stage, a single, fine-tuned, clock is synthesized by interpolating the two selected clocks.

Abstract: Embodiments of the present invention enable the matching of pull-up and pull-down driver strengths of a slave device (DDRII SDRAM), i.e., the P-channel/N-channel driver pull-up/pull-down Ron and also calibrates the P-channel/N-channel pull-up/pull-down drivers in their linear region of operation. Specifically, embodiments of the present invention may use the DDR-II Off Chip Driver (OCD) protocol for calibration, in addition to using circuit techniques to calibrate the slave driver pull-up Ron within 1 LSB of the pull-down Ron.

Abstract: The invention includes a method to adjust integrated circuit device I/O bus timing. In one embodiment, the method includes comparing an alignment between an edge of a first clock signal to a center of a data packet to produce an alignment offset signal and adjusting the first clock signal using a variable delay device in response to the alignment offset signal to substantially align the edge of the first clock signal to the center of the data packet. Other embodiments are claimed and described.

Abstract: In some embodiments, the invention includes a system having first and second modules and a circuit board including first and second module connectors to receive the first and second modules, respectively. A first path of conductors extends from the circuit board to the first module connector, to the first module, back to the first module connector, to the circuit board, to the second module connector and to the second module. The first path couples to chips of the first and second modules, and each of the chips include on die terminations, but only some of the chips include on die terminations that are enabled.

Abstract: A memory interface system comprising a differential control interface coupled with a first power supply, a common voltage supply and a buffer unit. The control interface is configured to drive a first and a second differential control output signal wherein the voltage output swing of the first and second differential control output signals is between a voltage output high level and the common voltage. The system also comprising a plurality of single-ended memory interfaces coupled with a second power supply, the common voltage supply and the buffer unit, wherein each memory interface is configured to drive a single-ended memory output signal to the common voltage to transfer a logic low, and the system also comprising the buffer unit coupled with the first power supply, the buffer unit configured to transfer data between the control interface and the memory interface.

Abstract: Embodiments of the present invention enable the matching of pull-up and pull-down driver strengths of a slave device (DDRII SDRAM), i.e., the P-channel/N-channel driver pull-up/pull-down Ron and also calibrates the P-channel/N-channel pull-up/pull-down drivers in their linear region of operation. Specifically, embodiments of the present invention may use the DDR-II Off Chip Driver (OCD) protocol for calibration, in addition to using circuit techniques to calibrate the slave driver pull-up Ron within 1 LSB of the pull-down Ron.

Abstract: The invention includes a method to communicate a data packet. At a second input of a variable delay device, a first clock signal having at least one edge is received. At a first input of a detector, a first data packet having data that defines a second clock signal is received. At a second input of the detector, an output of the variable delay device is received. The output of the variable delay device is then compared to the second clock signal to produce an offset signal. The first clock signal is adjusted as a function of the offset signal to produce an output of the variable delay device.