Abstract: In some embodiments, the invention includes a system having first and second modules; and a circuit board including first and second module connectors to receive the first and second modules, respectively. A first path of conductors extending from the circuit board to the first module connector, to the first module, back to the first module connector, to the circuit board, to the second module connector and to the second module, and wherein the first path in the first module couples to stubs for first and second chips of the first module and the first path in the second module couples to stubs for first and second chips of the first module; and each of the first and second chips include selectable on die terminations.

Abstract: Methods and devices for calibrating a driver on a slave device, using a master device driver as a load, are disclosed. A master reference driver is integrated on the same circuit as the master device driver, with both drivers having the same layout and geometry. The master reference driver is calibrated using a selected load impedance that includes the nominal slave device driver impedance and any other impedance elements. The same calibrated driver setting is concurrently applied to both the master driver and the master reference driver, while the slave device drives the master driver. The voltage at the master driver is compared to the voltage at the master reference driver, and the slave device driver impedance is adjusted until those voltages match. The resulting calibration of the slave device driver impedance is largely independent of the actual impedance of the master device driver.

Abstract: Operation of a video cassette player is facilitated by providing a VBI decoder which decodes information, such as title, channel, date, time and length of broadcast programs and utilizing the information in providing directory of the programs as well as control of the VCR. The video cassette player is also provided with a VBI encoder for inserting control as well as directory information into the tape, either in the VBI portions of the video track or in the control track.

Abstract: A first device delivers a clock offset message to a second device. The second device offsets its data transmission according to the clock offset message. A test pattern is transmitted from the second device to the first device. The first device then checks the received test pattern to determine whether the transmission was successful. The first device can then deliver an additional clock offset message to the second device to instruct the second device to offset its data transmission by a different value than was used previously. The second device again transmits the test pattern and the first device again checks the received pattern. By trying a number of clock offset values and determining which values result in successful transmissions of data, the first device can determine the optimal clock offset value and instruct the second device to use this value for all transmissions.

Abstract: A system for interfacing over a multi-drop bus comprising a single-ended control interface coupled with a first power supply, and a common supply and a plurality of single-ended memory interfaces coupled with a second power supply, the common supply and coupled directly to the control interface. The control interface is configured to drive a control output signal and the memory interface is configured to drive a memory output signal. The output signals are driven to the common supply to transfer a logic low.

Abstract: A memory interface system comprising a differential control interface coupled with a first power supply, a common voltage supply and a buffer unit. The control interface is configured to drive a first and a second differential control output signal wherein the voltage output swing of the first and second differential control output signals is between a voltage output high level and the common voltage. The system also comprising a plurality of single-ended memory interfaces coupled with a second power supply, the common voltage supply and the buffer unit, wherein each memory interface is configured to drive a single-ended memory output signal to the common voltage to transfer a logic low, and the system also comprising the buffer unit coupled with the first power supply, the buffer unit configured to transfer data between the control interface and the memory interface.

Abstract: A command controller reads and extracts predetermined key words and parameters from a configuration file. The command controller inserts digital data into a television signal according to the extracted predetermined key words and parameters. The command controller initiates a self-recovery operation to purge stored data and re-initialize the VBI inserter based on the extracted predetermined key words and parameters and time or access time. The command controller also extracts digital data from another video signal to be compared to stored diagnostic data or transmitted to another external source.

Abstract: Operation of a video cassette player is facilitated by providing a VBI decoder which decodes information, such as title, channel, date, time and length of broadcast programs and utilizing the information in providing directory of the programs as well as control of the VCR. The video cassette player is also provided with a VBI encoder for inserting control as well as directory information into the tape, either in the VBI portions of the video track or in the control track.

Abstract: Operation of a video cassette player is facilitated by providing a VBI decoder which decodes information, such as title, channel, date, time and length of broadcast programs and utilizing the information in providing directory of the programs as well as control of the VCR. The video cassette player is also provided with a VBI encoder for inserting control as well as directory information into the tape, either in the VBI portions of the video track or in the control track.

Abstract: In some embodiments, the invention includes a system having first and second modules; and a circuit board including first and second module connectors to receive the first and second modules, respectively. The system also includes a first clock path of conductors to carry a first clock signal to first, second, third, and fourth chips on the first module and then to first, second, third, and fourth chips on the second module; and a second clock path of conductors to carry a second clock signal to the first, second, third, and fourth chips on the second module and then to the first, second, third, and fourth chips on the first module.

Abstract: A method, system, and device capable of generating one or more clocks internally to detect, sample, and receive synchronous data streams and eliminate the need for corresponding external synchronization clocks for each data stream. One aspect of the clock generator provides a two-stage interpolation system. In a first stage, two clocks are selected which accurately detect a calibration data sample. In a second stage, a single, fine-tuned, clock is synthesized by interpolating the two selected clocks.

Abstract: In some embodiments, the invention includes a controller that has clock signal transmitters to transmit Clk signals and data signal transmitters to transmit Data signals. Multi-phase producing circuitry includes multiple taps to receive a clock signal and in response thereto to produce phases on the taps. Delay determining circuitry determines relative delays to be provided between the Clk signals and Data signals and to provide signals regarding the relative delays, and delay adjustment circuitry receives the signals regarding relative delays and select amongst the taps to achieve the relative delays between the Clk and Data signals. Other embodiments are described and claimed.

Abstract: In some embodiments, the invention includes a controller that has clock signal transmitters to transmit Clk signals and data signal transmitters to transmit Data signals. Multi-phase producing circuitry includes multiple taps to receive a clock signal and in response thereto to produce phases on the taps. Delay determining circuitry determines relative delays to be provided between the Clk signals and Data signals and to provide signals regarding the relative delays, and delay adjustment circuitry receives the signals regarding relative delays and select amongst the taps to achieve the relative delays between the Clk and Data signals. Other embodiments are described and claimed.

Abstract: In some embodiments, the invention includes a system having first and second modules; and a circuit board including first and second module connectors to receive the first and second modules, respectively. A first path of conductors extending from the circuit board to the first module connector, to the first module, back to the first module connector, to the circuit board, to the second module connector and to the second module, and wherein the first path in the first module couples to stubs for first and second chips of the first module and the first path in the second module couples to stubs for first and second chips of the first module; and each of the first and second chips include selectable on die terminations.

Abstract: In some embodiments, the invention includes a system having first and second modules and a circuit board including first and second module connectors to receive the first and second modules, respectively. A first path of conductors extends from the circuit board to the first module connector, to the first module, back to the first module connector, to the circuit board, to the second module connector and to the second module. The first path couples to chips of the first and second modules, and each of the chips include on die terminations, but only some of the chips include on die terminations that are enabled.

Abstract: In some embodiments, the invention includes a module including a circuit board and first and second groups of conductors supported by the circuit board. A first group of chips each include on die terminations that are enabled. At least some of a second group of chips have on die terminations that are disabled. The first group of chips are coupled to conductors of the first group of conductors and the second group of chips are coupled to conductors of the second group of conductors, and wherein the second group of conductors have higher impedances than do the first group of conductors.

Abstract: In some embodiments, the invention includes a system having first and second modules; and a circuit board including first and second module connectors to receive the first and second modules, respectively. The system also includes a first clock path of conductors to carry a first clock signal to first, second, third, and fourth chips on the first module and then to first, second, third, and fourth chips on the second module; and a second clock path of conductors to carry a second clock signal to the first, second, third, and fourth chips on the second module and then to the first, second, third, and fourth chips on the first module.

Abstract: An example embodiment of a method and apparatus for reducing back-to-back voltage glitch on a high speed bus is described. A pre-driver circuit receives an input voltage signal whose voltage level swings from a logically low voltage level to a logically high voltage level where the logically low voltage level approximately equals VSS and the logically high voltage level approximately equals VCC. The pre-driver circuit reduces the magnitude of the voltage swing to create a signal that when delivered to a driver transistor ensures that the driver transistor will operate in its saturation region even when the voltage on the high speed bus is at its minimum specified voltage. When the driver transistor operates in its saturation region it can sink a constant current and provide a high output impedance.

Abstract: Operation of a video cassette player is facilitated by providing a VBI decoder which decodes information, such as title, channel, date, time and length of broadcast programs and utilizing the information in providing directory of the programs as well as control of the VCR. The video cassette player is also provided with a VBI encoder for inserting control as well as directory information into the tape, either in the VBI portions of the video track or in the control track.

Abstract: Operation of a video cassette player is facilitated by providing a VBI decoder which decodes information, such as title, channel, date, time and length of broadcast programs and utilizing the information in providing directory of the programs as well as control of the VCR. The video cassette player is also provided with a VBI encoder for inserting control as well as directory information into the tape, either in the VBI portions of the video track or in the control track.