Abstract: A camera system includes a light source having a peak emission wavelength at room temperature in a near-infrared region, and an imaging device including a photoelectric conversion element that converts near-infrared light into an electric charge. An external quantum efficiency of the photoelectric conversion element has a first peak at a first wavelength longer than the peak emission wavelength, and the external quantum efficiency at the first wavelength is higher than the external quantum efficiency at the peak emission wavelength.

Abstract: A composition contains a naphthalocyanine derivative represented by the following formula: where R1 to R8 are independently an alkyl group and R9 to R12 are independently an aryl group, and at least one hydrogen atom in at least one selected from the group consisting of R9, R10, R11, and R12 is substituted by an electron-withdrawing group.

Abstract: According to one embodiment, a semiconductor integrated circuit includes a clock supply circuit, a first output circuit, and a second output circuit. The clock supply circuit outputs a first clock and a second clock, the first clock having a first period, the second clock having a second period that is 1/m times the first period. The m is a natural number of 2 or more. The first output circuit outputs a first signal indicating content of data to an outside when a first operation is performed and outputs a second signal having a toggle pattern based on the first clock to the outside when a second operation is performed. The second output circuit outputs an operation clock based on the first clock to the outside when the first operation is performed and outputs a sampling clock based on the second clock to the outside when the second operation is performed.

Abstract: According to one embodiment, a semiconductor integrated circuit includes a clock supply circuit, a first output circuit, and a second output circuit. The clock supply circuit outputs a first clock and a second clock, the first clock having a first period, the second clock having a second period that is 1/m times the first period. The m is a natural number of 2 or more. The first output circuit outputs a first signal indicating content of data to an outside when a first operation is performed and outputs a second signal having a toggle pattern based on the first clock to the outside when a second operation is performed. The second output circuit outputs an operation clock based on the first clock to the outside when the first operation is performed and outputs a sampling clock based on the second clock to the outside when the second operation is performed.

Abstract: A composition contains a phthalocyanine derivative represented by the following formula: where R1 to R8 are independently an alkyl group, M is Si, each of R9 and R10 is any one of substituents represented by the following formulas, R11 to R13 are independently an alkyl group, and R14 to R18 are independently an alkyl group or an aryl group:

Abstract: The light-emitting device includes a flexible substrate, a lower barrier layer positioned above the flexible substrate, a light-emitting element and a thin-film transistor controlling the light-emitting element positioned above the lower barrier layer, a first upper barrier layer positioned above the light-emitting element and including a first inorganic material, and a second upper barrier layer positioned above the thin-film transistor and including a second inorganic material. The first upper barrier layer and the second upper barrier layer are spaced from each other at least in a region between the light-emitting element and the thin-film transistor.

Abstract: The light-emitting device includes a flexible substrate, a lower barrier layer positioned above the flexible substrate, a light-emitting element and a thin-film transistor controlling the light-emitting element positioned above the lower barrier layer, a first upper barrier layer positioned above the light-emitting element and including a first inorganic material, and a second upper barrier layer positioned above the thin-film transistor and including a second inorganic material. The first upper barrier layer and the second upper barrier layer are spaced from each other at least in a region between the light-emitting element and the thin-film transistor.

Abstract: A storage device includes a plurality of non-volatile memory devices and a controller connected to the plurality of non-volatile memory devices. The controller is configured to enable the plurality of non-volatile memory devices simultaneously during a certain period of time, and broadcast an access command and an access destination address to the plurality of non-volatile memory devices during the certain period of time.

Abstract: A memory interface includes a first output circuit to be connected to the memory device for communication therewith, a first input circuit to be connected to the memory device for communication therewith, a first write circuit configured to process write data, a read circuit configured to process read data and a read strobe, a first delay adjustment circuit, a first switching circuit which is connected in a signal path between the first write circuit and the first delay adjustment circuit, and in a signal path between the first input circuit and the first delay adjustment circuit, and a second switching circuit which is connected in a signal path between the first delay adjustment circuit and the first output circuit, and in a signal path between the first delay adjustment circuit and the read circuit.

Abstract: A memory interface includes a first output circuit to be connected to the memory device for communication therewith, a first input circuit to be connected to the memory device for communication therewith, a first write circuit configured to process write data, a read circuit configured to process read data and a read strobe, a first delay adjustment circuit, a first switching circuit which is connected in a signal path between the first write circuit and the first delay adjustment circuit, and in a signal path between the first input circuit and the first delay adjustment circuit, and a second switching circuit which is connected in a signal path between the first delay adjustment circuit and the first output circuit, and in a signal path between the first delay adjustment circuit and the read circuit.

Abstract: The light-emitting device includes a flexible substrate, a lower barrier layer positioned above the flexible substrate, a light-emitting element and a thin-film transistor controlling the light-emitting element positioned above the lower barrier layer, a first upper barrier layer positioned above the light-emitting element and including a first inorganic material, and a second upper barrier layer positioned above the thin-film transistor and including a second inorganic material. The first upper barrier layer and the second upper barrier layer are spaced from each other at least in a region between the light-emitting element and the thin-film transistor.

Abstract: The light-emitting device according to one aspect of the present disclosure includes a flexible substrate, a lower barrier layer positioned above the flexible substrate, a first light-emitting element and a second light-emitting element positioned above the lower barrier layer, a first upper barrier layer positioned above the first light-emitting element and including a first inorganic material, and a second upper barrier layer positioned above the second light-emitting element and including a second inorganic material. The first upper barrier layer and the second upper barrier layer are spaced from each other at least in a region between the first light-emitting element and the second light-emitting element.

Abstract: The light-emitting device according to one aspect of the present disclosure includes a flexible substrate, a lower barrier layer positioned above the flexible substrate, a first light-emitting element and a second light-emitting element positioned above the lower barrier layer, a first upper barrier layer positioned above the first light-emitting element and including a first inorganic material, and a second upper barrier layer positioned above the second light-emitting element and including a second inorganic material. The first upper barrier layer and the second upper barrier layer are spaced from each other at least in a region between the first light-emitting element and the second light-emitting element.

Abstract: A passive-matrix display of the disclosure includes a first electrode disposed over a substrate, a second electrode disposed over the first electrode and three-dimensionally intersecting the first electrode, a first auxiliary electrode disposed between the substrate and the first electrode, three-dimensionally intersecting the first electrode and being parallel to the second electrode, and a second auxiliary electrode parallel to the first auxiliary electrode and to the second electrode, the first electrode and the first auxiliary electrode being electrically connected by a first connection portion, and the second electrode and the second auxiliary electrode being connected by a plurality of second connection portions each disposed with at least one of the first electrodes therebetween. The passive-matrix display enables voltage drop and variation in brightness to be reduced by lowering the wiring resistance of the second electrode.

Abstract: In a display device according to the present disclosure, leader lines are led out from a display region to a leader region adjacent to the display region. In the leader region, metal portions are disposed between adjacent two of the plurality of leader lines with gaps. The gaps are formed between each of the metal portions and each of the adjacent two of the plurality of leader lines. A sealing layer covers display elements in the display region and covers the leader lines in a first sealing region of the leader region adjacent to the display region. A part of the sealing layer fills the gaps and adheres to each of the metal portions in the first sealing region.

Abstract: In a display device according to the present disclosure, leader lines are led out from a display region to a leader region adjacent to the display region. In the leader region, metal portions are disposed between adjacent two of the plurality of leader lines with gaps. The gaps are formed between each of the metal portions and each of the adjacent two of the plurality of leader lines. A sealing layer covers display elements in the display region and covers the leader lines in a first sealing region of the leader region adjacent to the display region. A part of the sealing layer fills the gaps and adheres to each of the metal portions in the first sealing region.

Abstract: A passive-matrix display of the disclosure includes a first electrode disposed over a substrate, a second electrode disposed over the first electrode and three-dimensionally intersecting the first electrode, a first auxiliary electrode disposed between the substrate and the first electrode, three-dimensionally intersecting the first electrode and being parallel to the second electrode, and a second auxiliary electrode parallel to the first auxiliary electrode and to the second electrode, the first electrode and the first auxiliary electrode being electrically connected by a first connection portion, and the second electrode and the second auxiliary electrode being connected by a plurality of second connection portions each disposed with at least one of the first electrodes therebetween. The passive-matrix display enables voltage drop and variation in brightness to be reduced by lowering the wiring resistance of the second electrode.

Abstract: According to one embodiment, a memory access circuit includes a PLL, a phy-clock tree, first, second, and master DLLs, and first and second PDs. The PLL generates a PLL output locked to a reference frequency. The phy-clock tree delays the PLL output and generates a reference clock signal. The first DLL corrects a clock skew between reference and system clock signals, and generates a source of the system clock signal. The second DLL corrects a clock skew between reference clock and phy-clock signals, and generates a source of the phy-clock signal. The first and second PDs detect a phase difference, and generate first and second detection signals. The master DLL counts the reference clock signal and generates a delay correction signal. The first and second DLLs determine a correction direction and a correction amount based on first and second detection and delay correction signals, respectively.

Abstract: According to one embodiment, a timing adjustment circuit for a memory interface is presented. The circuit is provided with a gate circuit, an original gate signal generation circuit, a high impedance prevention unit, an impedance control unit and a gate leveling circuit. The gate circuit performs gating of a data strobe signal outputted from a memory. The original gate signal generation circuit generates an original gate signal based on information of a read latency and a burst length. The high impedance prevention unit to prevent the data strobe signal from being in a high impedance state. The impedance control unit controls execution and release of operation of the high impedance prevention unit. The gate leveling circuit outputs a timing adjusted gate signal to the gate circuit based on the original gate signal and the data strobe signal.

Abstract: According to one embodiment, a memory access circuit includes a PLL, a phy-clock tree, first, second, and master DLLs, and first and second PDs. The PLL generates a PLL output locked to a reference frequency. The phy-clock tree delays the PLL output and generates a reference clock signal. The first DLL corrects a clock skew between reference and system clock signals, and generates a source of the system clock signal. The second DLL corrects a clock skew between reference clock and phy-clock signals, and generates a source of the phy-clock signal. The first and second PDs detect a phase difference, and generate first and second detection signals. The master DLL counts the reference clock signal and generates a delay correction signal. The first and second DLLs determine a correction direction and a correction amount based on first and second detection and delay correction signals, respectively.