Patents by Inventor Hiroaki Ishiwata

Hiroaki Ishiwata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6661045
    Abstract: A photodiode and a read gate are formed within an element region. A p+ type punch-through preventing region is not formed immediately under an n-type signal accumulating region of a photodiode. The n-type signal accumulating region is formed within a p-type semiconductor substrate. The p+ type punch-through preventing region is formed over the entire element region. The p+ type punch-through preventing region is also formed immediately under an insulative isolation layer in order to prevent punch-through between elements. A p+ type punch-through stopper is formed immediately under an n-type first semiconductor region.
    Type: Grant
    Filed: June 28, 2001
    Date of Patent: December 9, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroaki Ishiwata
  • Patent number: 6521925
    Abstract: A solid-state image sensor comprises a photodiode which is provided in a p-type substrate or a p-type well and composed of a first n-type region for storing photoelectrically converted signal charges, a gate electrode provided above the substrate or well so as to be adjacent to one end of the photodiode, and a n-type drain provided at the surface of the substrate or well opposite to the photodiode, with the gate electrode interviewing therebetween. There is provided a second n-type region which is formed so as to be in contact with the upper part of the first n-type region on the gate electrode side and one end of which is formed to self-align with one end of the gate electrode to be part of the photodiode. This construction prevents the short-channel effect of the signal read transistor section and reduces or eradicates the left-over signal charges stored in the photodiode, thereby reducing noise and improving the sensitivity of the sensor.
    Type: Grant
    Filed: March 30, 2000
    Date of Patent: February 18, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akiko Mori, Hisanori Ihara, Tetsuya Yamaguchi, Hiroaki Ishiwata, Hidetoshi Nozaki
  • Patent number: 6504193
    Abstract: Part of a photodiode layer extends to a position under a gate electrode. The photodiode layer and a drain layer are separated by a punch-through stopper region. A surface shield layer is formed on the photodiode layer. When a voltage is applied to the gate electrode, the charge accumulated in the photodiode layer is transferred to the drain region via a channel formed under the gate electrode, not being affected by a potential barrier in the surface shield layer.
    Type: Grant
    Filed: June 29, 2000
    Date of Patent: January 7, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroaki Ishiwata, Yoshinori Iida
  • Patent number: 6344666
    Abstract: In an amplifier-type solid-state image sensor device, each unit cell comprises a photoconverter and a signal scanning circuit in an image sensing region on a semiconductor substrate, a metal film has an opening region for defining regions where light is radiated in the photoconverters of the unit cells, and a center position of the opening region of the metal film is displaced to the side of the center of the image sensing region with respect to a center portion of the photoconverter, so that the amount of light entering the center of the semiconductor chip and the peripheral portions of the semiconductor chip can be made equal, thereby obtaining substantially the same sensitivity at the center and peripheral portions of the semiconductor chip.
    Type: Grant
    Filed: September 29, 1999
    Date of Patent: February 5, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tetsuya Yamaguchi, Hisanori Ihara, Hiroaki Ishiwata, Akiko Mori
  • Publication number: 20020001039
    Abstract: A photodiode and a read gate are formed within an element region. A p+ type punch-through preventing region is not formed immediately under an n-type signal accumulating region of a photodiode. The n-type signal accumulating region is formed within a p-type semiconductor substrate. The p+ type punch-through preventing region is formed over the entire element region. The p+ type punch-through preventing region is also formed immediately under an insulative isolation layer in order to prevent punch-through between elements. A p+ type punch-through stopper is formed immediately under an n-type first semiconductor region.
    Type: Application
    Filed: June 28, 2001
    Publication date: January 3, 2002
    Inventor: Hiroaki Ishiwata