Abstract: Disclosed herein is a semiconductor device including a multi-level wiring structure that includes a lower-level wiring, an upper-level wiring and an interlayer insulating film between the lower-level and upper-level wirings. The device further includes a plurality of bit lines for a plurality of memory cells, and each of the bit lines includes a first portion that is formed as the lower-level wiring and a second portion that is electrically connected in series to the first portion and formed as the upper-level wiring.

Abstract: Disclosed herein is a semiconductor device including a multi-level wiring structure that includes a lower-level wiring, an upper-level wiring and an interlayer insulating film between the lower-level and upper-level wirings. The device further includes a plurality of bit lines for a plurality of memory cells, and each of the bit lines includes a first portion that is formed as the lower-level wiring and a second portion that is electrically connected in series to the first portion and formed as the upper-level wiring.

Abstract: Plural nonvolatile address storing circuits hold address data. A serial transfer circuit sequentially transfers the address data stored in each of the nonvolatile address storing circuits. A serial reception circuit sequentially receives the address data transferred by the serial transfer circuit. An address latch circuit holds the address data received by the serial reception circuit. An address comparison circuit compares each of the address data stored in the address latch circuit with an input address, and determines whether each address data coincides with the input address.

Abstract: Cyclopentanone 1,2-monooxygenase (CPMO) from Comamonas (previously Pseudomonas) sp. strain NCIMB 9872 carries out the second step of a degradation pathway that allows the bacterium to use cyclopentanol as a sole carbon source for growth. In the present invention there is reported the localization of the CPMO-encoding gene (cpnB) on a 4.3-kb SphI fragment, the determination of its sequence. The 550-amino acid CPMO polypeptide (Mr, 62,111) encoded by the gene was found to have 36.5% identity with the sequence of cyclohexanone 1,2-monooxygenase (CHMO) of Acinetobacter sp. strain NCIMB 9871. The 62-kDa CPMO was expressed in E. coli as an IPTG-inducible protein.

Abstract: An address generating circuit includes a first carry look-ahead circuit for performing an operation using an inputted first carry and a first address and outputting a first output address and a first output carry respectively as a first operation result, a second carry look-ahead circuit for performing an operation using a carry fixed to 0 and a second address and outputting a second output address and a second output carry respectively as a second operation result, a third carry look-ahead circuit for performing an operation using a carry fixed to 1 and the second address and outputting a third output address and a third output carry respectively as a third operation result, and a first select circuit for selecting either of the second and third operation results based on the first output carry and outputting the selected operation result.

Abstract: The invention relates to a new strain of Pseudomonas putida (designated as HI-70) and to the isolation, cloning, and sequencing of a cyclododecanone monooxygenase-encoding gene (named cdnB) from said strain. The invention also relates to a new cyclododecanone monooxygenase and to a method of use of the cyclododecanone monooxygenase-encoding gene.

Abstract: The invention relates to a new strain of Pseudomonas putida (designated as HI-70) and to the isolation, cloning, and sequencing of a cyclododecanone monooxygenase-encoding gene (named cdnB) from said strain. The invention also relates to a new cyclododecanone monooxygenase and to a method of use of the cyclododecanone monooxygenase-encoding gene.

Abstract: Cyclopentanone 1,2-monooxygenase (CPMO) from Comamonas (previously Pseudomonas) sp. strain NCIMB 9872 carries out the second step of a degradation pathway that allows the bacterium to use cyclopentanol as a sole carbon source for growth. In the present invention there is reported the localization of the CPMO-encoding gene (cpnB) on a 4.3-kb SphI fragment, the determination of its sequence. The 550-amino acid CPMO polypeptide (Mr, 62,111) encoded by the gene was found to have 36.5% identity with the sequence of cyclohexanone 1,2-monooxygenase (CHMO) of Acinetobacter sp. strain NCIMB 9871. The 62-kDa CPMO was expressed in E. coli as an IPTG-inducible protein.

Abstract: The invention relates to a new strain of Pseudomonas putida (designated as HI-70) and to the isolation, cloning, and sequencing of a cyclododecanone monooxygenase-encoding gene (named cdnB) from said strain. The invention also relates to a new cyclododecanone monooxygenase and to a method of use of the cyclododecanone monooxygenase-encoding gene.

Abstract: Cyclopentanone 1,2-monooxygenase (CPMO) from Comamonas (previously Pseudomonas) sp. strain NCIMB 9872 carries out the second step of a degradation pathway that allows the bacterium to use cyclopentanol as a sole carbon source for growth. In the present invention there is reported the localization of the CPMO-encoding gene (cpnB) on a 4.3-kb SphI fragment, the determination of its sequence. The 550-amino acid CPMO polypeptide (Mt, 62,111) encoded by the gene was found to have 36.5% identity with the sequence of cyclohexanone 1,2-monooxygenase (CHMO) of Acinetobacter sp. strain NCIMB 9871. The 62-kDa CPMO was expressed in E. coli as an IPTG-inducible protein.

Abstract: The invention relates to a new strain of Pseudomonas putida (designated as HI-70) and to the isolation, cloning, and sequencing of a cyclododecanone monooxygenase-encoding gene (named cdnB) from said strain. The invention also relates to a new cyclododecanone monooxygenase and to a method of use of the cyclododecanone monooxygenase-encoding gene.

Abstract: Cyclopentanone 1,2-monooxygenase (CPMO) from Comamonas (previously Pseudomonas) sp. strain NCIMB 9872 carries out the second step of a degradation pathway that allows the bacterium to use cyclopentanol as a sole carbon source for growth. In the present invention there is reported the localization of the CPMO-encoding gene (cpnB) on a 4.3-kb SphI fragment, the determination of its sequence. The 550-amino acid CPMO polypeptide (Mt, 62,111) encoded by the gene was found to have 36.5% identity with the sequence of cyclohexanone 1,2-monooxygenase (CHMO) of Acinetobacter sp. strain NCIMB 9871. The 62-kDa CPMO was expressed in E. coli as an IPTG-inducible protein.

Abstract: A semiconductor integrated circuit so configured to stop the supplying of an electric power to a logic circuit in a standby mode, thereby to realize a low power consumption, includes a latch circuit characterized in that as the control signal a clock signal is supplied in the active mode, and a signal for creating an information hold condition is supplied in the standby mode, and in that MOSFETs applied with a control signal include a first conductivity type MOSFET having a high threshold and a second conductivity type MOSFET having a low threshold, a voltage amplitude of the control signal being larger than a power supply voltage. The semiconductor integrated circuit can be realized in that the high speed operation in the active mode and the low power consumption in the standby mode are compatible with each other, and it is sufficient if a power switch for the logic circuit is inserted at only either of the high level power supply voltage line side and the low level power supply voltage line side.

Abstract: A semiconductor integrated circuit so configured to stop the supplying of an electric power to a logic circuit in a standby mode, thereby to realize a low power consumption, includes a latch circuit characterized in that as the control signal a clock signal is supplied in the active mode, and a signal for creating an information hold condition is supplied in the standby mode, and in that MOSFETs applied with a control signal include a first conductivity type MOSFET having a high threshold and a second conductivity type MOSFET having a low threshold, a voltage amplitude of the control signal being larger than a power supply voltage. The semiconductor integrated circuit can be realized in that the high speed operation in the active mode and the low power consumption in the standby mode are compatible with each other, and it is sufficient if a power switch for the logic circuit is inserted at only either of the high level power supply voltage line side and the low level power supply voltage line side.

Abstract: A latch type sense amplifier circuit comprises first and second latch circuits which output the same output signals when a potential difference between a bit line pair is equal to or greater than a predetermined value. The first and second latch circuits output different output signals when the potential difference between the bit line pair is less than the predetermined value. The latch type sense amplifier circuit further comprises a comparison result signal generating circuit which compares the output signals from the first and second latch circuits and outputs a signal indicative of the comparison result.

Abstract: A semiconductor integrated circuit includes a power supply circuit having a global source line VCC, a local source line QVCC coupled to VCC by a source switching transistor, and a global ground line VSS, a low-threshold logic (combinational) circuit connected between QVCC and VSS, and a data storage (sequential) circuit, connected between VCC and VSS. The data storage circuit includes a low-threshold input section for receiving data from the logic circuit and a high-threshold latch section for latching the data received by the input section. Mode switching transistors are inserted between the low-threshold logic circuit and VSS, between low-threshold input section and VCC and between the low-threshold input section and VSS, for effecting a sleep mode of the semiconductor integrated circuit. Low power dissipation is maintained with a reduced circuit scale.

Abstract: In a semiconductor memory device, a plurality of memory cells are arranged in a matrix. Each of the plurality of memory cells is connected to one of a plurality of word lines and is connected to one of a plurality of bit lines such that a plurality of columns are formed from the plurality of memory cells. A word line selecting section selects one of the plurality of word lines based on a first address. A first column selector selects one of the plurality of columns as a first column based on the first address. A second column selector selects another one of the plurality of columns as a second column based on a second address. An address data of a predetermined portion of the first address is not equal to an address data of the second address. An input/output section includes a first sense amplifier and a first buffer.

Abstract: An inverter circuit has first and second input terminals for receiving a complementary input signals, first and second output terminals for outputting a complementary output signals generated from the complementary input signals, and a pair of rectifier sections each for flowing the charge stored on a higher-potential side of the output terminals to a lower-potential said of the output terminals, for saving power dissipation.

Abstract: A square measure of a basic cell and a basic circuit cell of a semiconductor device used a SOI.cndot.CMOS technology is reduced. In the semiconductor device used a SOI.cndot.CMOS technology, the basic cells constituted by two pieces of PMOS and two pieces of NMOS are arranged in order of the PMOS, the PMOS, the NMOS and NMOS or NMOS, the NMOS, the PMOS and the PMOS in a row, and the diffused layer of a portion on which the PMOS and the NMOS adjoin are formed in a manner to adjoin directly. Moreover, the power source wiring and the grounding wiring are arranged around the basic cell in a manner to being held in common with the adjacent cells, and at least one of PMOS diffused layers is arranged so as to be able to be connected with a power source wiring through a contact directly and at least one of NMOS diffused layers is arranged so as to be able to be connected with a grounding wiring through a contact directly.

Abstract: In a CMOS SRAM cell formed on an SOI substrate and including a flip-flop having first and second NMOS and PMOS transistors, transfer gates having first and seconf MOS transistors, and a word line section, characterized in that:the word line section extends along a predetermined direction; that source and drain diffusion layer regions of the first and second NMOS and PMOS transistors are arranged along the predetermined direction, and gates of these NMOS and PMOS transistors are arranged on channel regions thereof in a direction perpendicular to the predetermined direction; that the gates of the first and second NMOS transistors are electrically connected to the gates of the first and second PMOS transistors, respectively; and that in regions between the gates of the first and second NMOS transistors on the channel regions and the gates of the first and second PMOS transistors on the channel regions, each of the drain diffusion layer regions of the fisrt and second NMOS and PMOS transistors, and each one of th