Abstract: An anti-cancer agent contains a phosphine transition metal complex having a ferrocene skeleton, the complex being represented by general formula (3) below: (wherein R1, R2, R3, and R4 each represent a linear or branched alkyl group, a cycloalkyl group, an alkoxy group, an aryl group, or an aralkyl group; A represents a linear or branched alkyl group, a phenyl group, or a hydrogen atom; M1 represents a transition metal atom selected from the group consisting of gold, copper, platinum, and silver; and X1 represents an anion).

Abstract: The present invention aims to provide a substrate for mounting an IC chip, on which an optical signal passing region is formed and which can suppress a transmission loss in an optical signal and transmit an optical signal more positively with high reliability. The substrate for mounting an IC chip according to the present invention is a substrate for mounting an IC chip, in which a conductor circuit and an insulating layer are laminated in alternate fashion and in repetition on both faces of a substrate and an optical element is mounted on the substrate. Herein, the substrate for mounting an IC chip includes an optical signal passing region, and a microlens arranged on an end portion of the optical signal passing region on the opposite side from the optical element.

Abstract: A semiconductor device able to improve data retaining characteristics and decrease power consumption, further able to realize more unrestricted system without increasing excessive circuits, and having the following: an ALPG receiving a start signal and a mode selection signal to generate commands and addresses with respect to a DRAM circuit with the predetermined patterns in accordance with modes, and outputting an ending signal when ending a pattern generating processing in each of modes; an ECC circuit receiving a start signal and a mode selection signal indicating a parity generation mode to generate a parity based on data read from the DRAM circuit, receiving the start signal and a mode selection signal indicating an error correction mode to perform an error correction with respect to data read from the DRAM circuit based on the parity generated in the parity generation mode and outputting data after correcting; and an interface circuit.

Abstract: A device for optical communication comprising; at least a conductor circuit and an insulating layer formed and laminated, an optical circuit and an optical path for transmitting an optical signal; and an optical element or a package substrate on which an optical element is mounted, wherein an optical path converting member is disposed at the optical path for transmitting an optical signal so as to transmit an optical signal between the optical element and the optical circuit, the optical path converting member comprises a lens and an optical path conversion mirror having an entrance surface, an exit surface and a reflection surface, and the lens is provided at least one position selected from the entrance surface, the exit surface, and inside of the optical path conversion mirror.

Abstract: A multilayer printed circuit board according to the present invention is a multilayer printed circuit board where a plurality of insulating layers, a conductor circuit and an optical circuit are formed and layered and an optical element is mounted, wherein the above described optical circuit is formed between the above described insulating layers.

Abstract: A semiconductor memory device according to the present invention includes a BIST circuit for evaluating quality of each of memory cells and a buffer (memory) for storing address information of abnormal cells which information is sent from the BIST circuit, the BIST circuit and the buffer being mounted on the same chip as a DRAM. A repair search circuit determines a minimum of address information required to determine redundant cells for replacement in the address information of the abnormal cells which information is sent from the BIST circuit, and stores only the determined address information in the buffer. Since only a minimum of address pairs required determining the redundant cells for repairing the abnormal cells are stored in the buffer, circuit scale is reduced. Further, processing for calculating address information of the redundant cells for repairing the abnormal cells can be performed at high speed.

Abstract: The present invention aims to provide a substrate for mounting an IC chip, on which an optical signal passing region is formed and which can suppress a transmission loss in an optical signal and transmit an optical signal more positively with high reliability. The substrate for mounting an IC chip according to the present invention is a substrate for mounting an IC chip, in which a conductor circuit and an insulating layer are laminated in alternate fashion and in repetition on both faces of a substrate and an optical element is mounted on the substrate. Herein, the substrate for mounting an IC chip includes an optical signal passing region, and a microlens arranged on an end portion of the optical signal passing region on the opposite side from the optical element.

Abstract: The present invention is to provide a multipotent cell wherein the sufficient amount necessary can be stably and conveniently supplied with a minimum invasion, that will not cause rejection at the time of cell transplantation, that has a potential to differentiate into various cells such as mesenchymal cells including bone, cartilage, skeletal muscle and fat, endothelial cells, myocardial cells, neurons, mesenchymal cells, myocardial cells, endothelial cells, neurons induced to differentiate from the multipotent cell, and a therapeutic agent/treating method comprising these as active ingredient. Peripheral blood mononuclear cells (PMBC) are cultured on fibronectin-coated plastic plates for 7 to 10 days. The generating cell population with a fibroblast-like morphology is derived from circulating CD14+ monocyte, with a unique phenotype of CD14+CD45+CD34+ type I collagen+.

Abstract: Control of cell cycle is important in crop breeding, and it is demanded to develop, through the control, techniques for modifying cell growth in plants, techniques for modifying the development/differentiation of plant individuals and plant genes for use therein. It has been successfully disclosed that plant gene 3Rmyb is a factor indispensable for the multiplication of plant cells. Thus, there are provided, with the gene as a target, techniques for modifying the multiplication of plant cells and techniques for modifying the development/differentiation of plant individuals, and there can be obtained plants and plant cells retaining modified cell growth and development/differentiation. These enable development of plants with desirable properties, such as specified organ enlargement, male sterility or improved stress resistance.

Abstract: A memory unit includes unit blocks laid out to form a block matrix. Each of the unit blocks has a plurality of memory cells laid out to form a cell matrix and redundant lines including redundant memory cells each used for repairing an abnormal memory cell. Every plurality of unit blocks forms a two-dimensional group oriented in a first direction and a second direction, and the redundant lines connected in the first and second directions are shared by the unit blocks pertaining to the two-dimensional group. Self-repair means embedded in the same chip as the memory unit stores only a minimum number of address pairs in storage means provided for each of the unit blocks as address pairs required for determining a redundant line to be used for repairing an abnormal memory cell and, then, finds a redundant line to be used for repairing an abnormal memory cell for each of the unit blocks pertaining to the two-dimensional group on the basis of the address pairs stored in the storage means.

Abstract: In a memory unit provided by the present invention, unit blocks are laid out to form a block matrix. Each of the unit blocks has a plurality of memory cells arranged to form a cell matrix and a redundant line including a redundant memory cell. A plurality of unit blocks in the block matrix forms a one-dimensional group oriented in a first or second direction so that unit blocks pertaining to each one-dimensional group share a redundant line. Self-repair means embedded in the same chip as the memory unit stores only a minimum number of address pairs required for determining a redundant line to be used for repairing an abnormal memory cell for each unit block in storage means. The address of the redundant line to be used for repairing an abnormal memory is then found for each unit block on the basis of the minimum number of address pairs stored in the storage means. By storing only minimum required address information as such, a small size of the storage means and, hence, small circuit scales are sufficient.

Abstract: An object of the present invention is to provide a substrate for mounting an IC chip which is a component for optical communication having an IC chip and an optical component integrally provided thereon, which can ensure a short distance between the IC chip and the optical component, which is excellent in electric signal transmission reliability and which can transmit optical signal through an optical path for transmitting optical signal. The substrate for mounting an IC chip of the present invention is a substrate for mounting an IC chip comprising: a substrate and, as serially built up on both faces thereof, a conductor circuit and an interlaminar insulating layer in an alternate fashion and in repetition; a solder resist layer formed as an outermost layer; and an optical element mounted thereto, wherein an optical path for transmitting optical signal, which penetrates the substrate for mounting an IC chip, is disposed.

Abstract: A semiconductor device able to improve data retaining characteristics and decrease power consumption, further able to realize more unrestricted system without increasing excessive circuits, and having the following: an ALPG receiving a start signal and a mode selection signal to generate commands and addresses with respect to a DRAM circuit with the predetermined patterns in accordance with modes, and outputting an ending signal when ending a pattern generating processing in each of modes; an ECC circuit receiving a start signal and a mode selection signal indicating a parity generation mode to generate a parity based on data read from the DRAM circuit, receiving the start signal and a mode selection signal indicating an error correction mode to perform an error correction with respect to data read from the DRAM circuit based on the parity generated in the parity generation mode and outputting data after correcting; and an interface circuit.

Abstract: In a memory unit provided by the present invention, unit blocks are laid out to form a block matrix. Each of the unit blocks has a plurality of memory cells arranged to form a cell matrix and a redundant line including a redundant memory cell. A plurality of unit blocks in the block matrix forms a one-dimensional group oriented in a first or second direction so that unit blocks pertaining to each one-dimensional group share a redundant line. Self-repair means embedded in the same chip as the memory unit stores only a minimum number of address pairs required for determining a redundant line to be used for repairing an abnormal memory cell for each unit block in storage means. The address of the redundant line to be used for repairing an abnormal memory is then found for each unit block on the basis of the minimum number of address pairs stored in the storage means. By storing only minimum required address information as such, a small size of the storage means and, hence, small circuit scales are sufficient.

Abstract: A memory unit includes unit blocks laid out to form a block matrix. Each of the unit blocks has a plurality of memory cells laid out to form a cell matrix and redundant lines including redundant memory cells each used for repairing an abnormal memory cell. Every plurality of unit blocks forms a two-dimensional group oriented in a first direction and a second direction, and the redundant lines connected in the first and second directions are shared by the unit blocks pertaining to the two-dimensional group. Self-repair means embedded in the same chip as the memory unit stores only a minimum number of address pairs in storage means provided for each of the unit blocks as address pairs required for determining a redundant line to be used for repairing an abnormal memory cell and, then, finds a redundant line to be used for repairing an abnormal memory cell for each of the unit blocks pertaining to the two-dimensional group on the basis of the address pairs stored in the storage means.

Abstract: A semiconductor memory device according to the present invention includes a BIST circuit for evaluating quality of each of memory cells and a buffer (memory) for storing address information of abnormal cells which information is sent from the BIST circuit, the BIST circuit and the buffer being mounted on the same chip as a DRAM. A repair search circuit determines a minimum of address information required to determine redundant cells for replacement in the address information of the abnormal cells which information is sent from the BIST circuit, and stores only the determined address information in the buffer. Since only a minimum of address pairs required determining the redundant cells for repairing the abnormal cells are stored in the buffer, circuit scale is reduced. Further, processing for calculating address information of the redundant cells for repairing the abnormal cells can be performed at high speed.

Abstract: A female screw portion is formed around an axis of a rotor of a step motor to penetrate through the rotor in an axial direction of the rotor. A male screw portion is formed on an outer peripheral surface of a screw shaft so that the screw shaft is screwed into the female screw portion. The screw shaft is inserted in a ring rod, and a connection clip portion is connected to the ring rod. When the rotor rotates, the ring rod reciprocates linearly in the axial direction of the rotor, and vertical fins rock in the axial direction of the rotor.

Abstract: A rear body structure of a vehicle body has a crushable reinforcement disposed inside a rear fender panel and extending in a lengthwise direction for structurally reinforcing a rear body portion of the vertical body. The crushable reinforcement is controlled so as to crush in an intended pattern during a rear-end collision. Consequently, the impact energy generated during the rear-end collision and applied to the automotive vehicle body is absorbed.

Abstract: The invention relates to enkephalin analogs of the formula ##STR1## wherein in case of X is D-Val, D-Phe, Pro, D-Met, D-Met(O), D-Leu, D-Glu, D-Glu(Obzl), D-Lys, D-Lys(Z), or D-Arg,Y is Gly or Phe; andR isa) a direct bond,b) an alkylene group having from 1 to 6 carbon atoms,c) o-, m-, or p-phenylene group,d) a cycloalkane; orwherein in case ofX is D-Ala,Y is Phe; andR isa) a direct bond,b) an alkylene group having from 1 to 6 carbon atoms,c) o-, m-, or p-phenylene group, ord) a cycloalkane,its salts and hydrates, as well as a therapeutic composition containing at least one of the enkephalin analogs, as an effective component.

Abstract: An automobile rear underbody structure which comprises generally elongated side frames extending in a direction lengthwise of an automobile body structure and each having a front and rear frame portions. The rear frame portion of each side frame lies in a level offset upwardly relative to the front frame portion. The rear frame portion has a depressed zone defined at a predetermined position thereof to permit the rear frame portion to bend downwardly when an external impact greater than a predetermined value is applied thereto.