Abstract: A sulfide solid electrolyte, which is able to adjust the morphology unavailable traditionally, or is readily adjusted so as to have a desired morphology, the sulfide solid electrolyte having a volume-based average particle diameter measured by laser diffraction particle size distribution measurement of 3 ?m or more and a specific surface area measured by the BET method of 20 m2/g or more; and a method of treating a sulfide solid electrolyte including the sulfide solid electrolyte being subjected to at least one mechanical treatment selected from disintegration and granulation.

Abstract: The present invention provides a thermoelectric conversion module which can utilize sunlight and solar heat by using high output charge-transport-type thermoelectric conversion elements.

Abstract: The present invention provides thermoelectric conversion elements and thermoelectric conversion modules which are possible to effectively use oxide materials having high Seebeck coefficient, and excellently improve their outputs. The present invention provides thermoelectric conversion elements which comprise at least a charge transport layer, thermoelectric conversion material layers and electrodes, wherein the charge transport layer comprises a graphite treated to dope charge-donating materials so that the graphite has an n-type semiconductor property, or a graphite treated to dope charge-accepting materials so that the graphite has a p-type semiconductor property, and provides thermoelectric conversion modules using the thermoelectric conversion elements.

Abstract: A thermoelectric conversion element comprising a thermoelectric conversion section and electrodes, wherein the thermoelectric conversion section includes at least: a thermoelectric conversion material section or a thermoelectric conversion material layer which is formed of a thermoelectric conversion material; and a charge transport section or a charge transport layer which is formed of a charge transport material having at least both semiconducting electric conduction properties and metallic electric conduction properties.

Abstract: The present invention provides a thermoelectric conversion module which can utilize sunlight and solar heat by using high output charge-transport-type thermoelectric conversion elements.

Abstract: The present invention provides thermoelectric conversion elements and thermoelectric conversion modules which are possible to effectively use oxide materials having high Seebeck coefficient, and excellently improve their outputs. The present invention provides thermoelectric conversion elements which comprise at least a charge transport layer, thermoelectric conversion material layers and electrodes, wherein the charge transport layer comprises a graphite treated to dope charge-donating materials so that the graphite has an n-type semiconductor property, or a graphite treated to dope charge-accepting materials so that the graphite has a p-type semiconductor property, and provides thermoelectric conversion modules using the thermoelectric conversion elements.

Abstract: The present invention realizes an efficient superscalar instruction issue and low power consumption at an instruction set including instructions with prefixes. An instruction fetch unit is adopted which determines whether an instruction code is of a prefix code or an instruction code other than it, and outputs the result of determination and the 16-bit instruction code. Along with it, decoders each of which decodes the instruction code, based on the result of determination, and decoders each of which decodes the prefix code, are disposed separately. Further, a prefix is supplied to each decoder prior to a fixed-length instruction code like 16 bits modified with it. A fixed-length instruction code following the prefix code is supplied to each decoder of the same pipeline as the decoder for the prefix code.

Abstract: The present invention realizes an efficient superscalar instruction issue and low power consumption at an instruction set including instructions with prefixes. An instruction fetch unit is adopted which determines whether an instruction code is of a prefix code or an instruction code other than it, and outputs the result of determination and the 16-bit instruction code. Along with it, decoders each of which decodes the instruction code, based on the result of determination, and decoders each of which decodes the prefix code, are disposed separately. Further, a prefix is supplied to each decoder prior to a fixed-length instruction code like 16 bits modified with it. A fixed-length instruction code following the prefix code is supplied to each decoder of the same pipeline as the decoder for the prefix code.

Abstract: A thermoelectric conversion element comprising a thermoelectric conversion section and electrodes, wherein the thermoelectric conversion section includes at least: a thermoelectric conversion material section or a thermoelectric conversion material layer which is formed of a thermoelectric conversion material; and a charge transport section or a charge transport layer which is formed of a charge transport material having at least both semiconducting electric conduction properties and metallic electric conduction properties.

Abstract: An information processing device is provided, in which a bit operation is performed without degradation in performance of a bus. An information processing device includes a CPU which fetches and executes an instruction, and a peripheral module which includes internally a register rewritable by the CPU, and is coupled to the CPU via a bus. The CPU has a function of issuing a bus command for commanding a bitwise write operation to the register comprised in the peripheral module, in order to execute a bit operation command fetched. When the bus command is issued, the peripheral module executes a bitwise write operation for the register. Since the CPU does not need to lock the bus after the bus command is issued, a bit operation can be performed without degradation in performance of the bus.

Abstract: A semiconductor memory device having high integration, low power consumption and high operation speed. The memory device includes a sense amplifier circuit having plural pull-down circuits and a pull-up circuit. A transistor constituting one of the plural pull-down circuits has a larger constant than that of a transistor constituting the other pull-down circuits, for example, a channel length and a channel width. The pull-down circuit having the larger constant transistor is activated earlier than the other pull-down circuits and the pull-up circuit, which are activated to conduct reading. The data line and the earlier driven pull-down circuit are connected by an NMOS transistor and the NMOS transistor is activated or inactivated to control the activation or inactivation of the pull-down circuit.

Abstract: Disclosed is a timing control circuit which receives a first clock having a period T1 and a group of second clocks of L different phases (where L is a positive integer) spaced apart from each other at substantially equal intervals and which generates a fine timing signal delayed from the rising edge of the first clock by a delay td of approximately td=m·T1+n·(T2/L), where m and n are non-negative integers. The timing control circuit has a coarse delay circuit and a fine delay circuit. The coarse delay circuit counts the rising edges of the first clock after an activate signal is activated and generates a coarse timing signal delayed from the first clock by approximately m·T1. The fine delay circuit has a circuit which, after the activate signal is activated, detects a second clock, which has a rising edge that immediately follows the rising edge of the first clock, from among the group of L-phase second clocks.

Abstract: An image forming apparatus includes a fusing device; a developing device; a partition wall disposed between the fusing device and the developing device, wherein the partition wall includes a Peltier element for transferring heat from the developing device to the fusing device and a cooling heat storage member disposed nearer to the developing device than the Peltier element.

Abstract: The present invention realizes an efficient superscalar instruction issue and low power consumption at an instruction set including instructions with prefixes. An instruction fetch unit is adopted which determines whether an instruction code is of a prefix code or an instruction code other than it, and outputs the result of determination and the 16-bit instruction code. Along with it, decoders each of which decodes the instruction code, based on the result of determination, and decoders each of which decodes the prefix code, are disposed separately. Further, a prefix is supplied to each decoder prior to a fixed-length instruction code like 16 bits modified with it. A fixed-length instruction code following the prefix code is supplied to each decoder of the same pipeline as the decoder for the prefix code.

Abstract: A semiconductor memory device having high integration, low power consumption and high operation speed. The memory device includes a sense amplifier circuit having plural pull-down circuits and a pull-up circuit. A transistor constituting one of the plural pull-down circuits has a larger constant than that of a transistor constituting the other pull-down circuits, for example, a channel length and a channel width. The pull-down circuit having the larger constant transistor is activated earlier than the other pull-down circuits and the pull-up circuit, which are activated to conduct reading. The data line and the earlier driven pull-down circuit are connected by an NMOS transistor and the NMOS transistor is activated or inactivated to control the activation or inactivation of the pull-down circuit.

Abstract: Disclosed is a semiconductor device including a first clock generator that generates a first clock signal having a first period from an input clock signal, a second clock generator that generates a second clock signal having a second period from the input clock signal, and a timing generator that receives the first clock signal, the second clock signal, an activation signal from a command decoder and a selection signal for selecting the delay time from a timing register to produce a timing signal delayed as from activation of the activation signal by a delay equal to a sum of a time equal to a preset number m prescribed by the selection signal times the first period and a time equal to another preset number n prescribed by the selection signal times the second period. The timing register holds the values of m and n. These values are set in the timing register in an initialization sequence at the time of a mode register set command.

Abstract: A semiconductor memory device having high integration, low power consumption and high operation speed. The memory device includes a sense amplifier circuit having plural pull-down circuits and a pull-up circuit. A transistor constituting one of the plural pull-down circuits has a larger constant than that of a transistor constituting the other pull-down circuits, for example, a channel length and a channel width. The pull-down circuit having the larger constant transistor is activated earlier than the other pull-down circuits and the pull-up circuit, which are activated to conduct reading. The data line and the earlier driven pull-down circuit are connected by an NMOS transistor and the NMOS transistor is activated or inactivated to control the activation or inactivation of the pull-down circuit.

Abstract: A substrate voltage control technique that prevents the operating speed from being decreased and suppresses a leakage current due to a lower threshold voltage with respect to a low voltage use. Since a center value of the threshold voltages is detected by plural replica MOS transistors, and a substrate voltage is controlled to control a center value of the threshold voltages, thereby making it possible to satisfy a lower limit of the operating speed and an upper limit of a leakage current of the entire chip. On the other hand, the substrate voltage is dynamically controlled during the operation of the chip, thereby making it possible to decrease the center value of the threshold voltages when the chip operates to improve the speed, and to increase the center value of the threshold voltages after the operation of the chip to reduce the leakage current of the entire chip.

Abstract: Disclosed is a timing control circuit that receives a first clock having a period T1, a group of second clocks of L different phases spaced apart from each other at substantially equal intervals and selection signals m, n supplied thereto and generates a fine timing signal delayed from the rising edge of the first clock signal by a delay td of approximately td=m·T1+n·(T2/L). The timing control circuit includes a coarse delay circuit and a fine delay circuit. The coarse delay circuit includes a counter for counting a rising edge of the first clock signal after an activate signal is activated and generates a coarse timing signal whose amount of delay from the first clock signal is approximately m·T1.

Abstract: A substrate voltage control technique that prevents the operating speed from being decreased and suppresses a leakage current due to a lower threshold voltage with respect to a low voltage use. Since a center value of the threshold voltages is detected by plural replica MOS transistors, and a substrate voltage is controlled to control a center value of the threshold voltages, thereby making it possible to satisfy a lower limit of the operating speed and an upper limit of a leakage current of the entire chip. On the other hand, the substrate voltage is dynamically controlled during the operation of the chip, thereby making it possible to decrease the center value of the threshold voltages when the chip operates to improve the speed, and to increase the center value of the threshold voltages after the operation of the chip to reduce the leakage current of the entire chip.