Patents by Inventor Hiroaki Nitta
Hiroaki Nitta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12200870Abstract: A component mounting system includes a component mounting device (15) configured to mount a component (E) on a board (S), a component storage (20) configured to store a component containing member (200) configured to contain a plurality of the components to be mounted on the board by the component mounting device, and a controller (22) configured to control an order in which the component containing member is unloaded from the component storage. The controller is configured to control the order in which the component containing member is unloaded based on an unloading priority when a plurality of the component containing members are scheduled to be unloaded.Type: GrantFiled: March 29, 2019Date of Patent: January 14, 2025Assignee: YAMAHA HATSUDOKI KABUSHIKI KAISHAInventor: Hiroaki Nitta
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Publication number: 20230129516Abstract: A parts mounting system (100) includes a parts mounting device (15) configured to mount parts (E) on a board (S), a parts storage (20) configured to store the parts supplied to the parts mounting device, and a controller (30) configured or programmed to perform a control to detect whether or not an unloading order can be changed based on whether or not the parts can be supplied to the parts mounting device in time when an order in which the parts are unloaded from the parts storage is changed.Type: ApplicationFiled: March 2, 2020Publication date: April 27, 2023Applicant: YAMAHA HATSUDOKI KABUSHIKI KAISHAInventors: Hiroaki NITTA, Norimitsu SUZUKI, Toshihiro MICHIZOE
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Publication number: 20220174850Abstract: A component mounting system includes a component mounting device (15) configured to mount a component (E) on a board (S), a component storage (20) configured to store a component containing member (200) configured to contain a plurality of the components to be mounted on the board by the component mounting device, and a controller (22) configured to control an order in which the component containing member is unloaded from the component storage. The controller is configured to control the order in which the component containing member is unloaded based on an unloading priority when a plurality of the component containing members are scheduled to be unloaded.Type: ApplicationFiled: March 29, 2019Publication date: June 2, 2022Applicant: YAMAHA HATSUDOKI KABUSHIKI KAISHAInventor: Hiroaki NITTA
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Patent number: 11152247Abstract: A semiconductor device is provided in which a zener diode having a desired breakdown voltage and a capacitor in which voltage dependence of capacitance is reduced are mounted together, and various circuits are realized. The semiconductor device includes: a semiconductor layer; a first conductivity type well that is arranged in a first region of the semiconductor layer; a first conductivity type first impurity diffusion region that is arranged in the well; a first conductivity type second impurity diffusion region that is arranged in a second region of the semiconductor layer; an insulating film that is arranged on the second impurity diffusion region; an electrode that is arranged on the insulating film; and a second conductivity type third impurity diffusion region that is arranged at least on the first impurity diffusion region.Type: GrantFiled: June 19, 2020Date of Patent: October 19, 2021Assignee: SEIKO EPSON CORPORATIONInventors: Kazunobu Kuwazawa, Shigeyuki Sakuma, Hiroaki Nitta, Mitsuo Sekisawa, Takehiro Endo
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Patent number: 10958263Abstract: Provided is a drive control device including: a first output node coupled to a gate node of a high-side transistor; a second output node coupled to a drive node; a first transistor provided between a first power supply node and the first output node; and a current limiting circuit and a second transistor provided in series between the first output node and the second output node, in which the current limiting circuit limits a current from the drive node toward the first output node to a predetermined value. The current limiting circuit is, for example, a transistor having a direction opposite to that of the second transistor.Type: GrantFiled: March 10, 2020Date of Patent: March 23, 2021Assignee: SEIKO EPSON CORPORATIONInventors: Toshimichi Yamada, Tatsuro Shinmitsu, Kazuhiko Okawa, Hiroaki Nitta, Masahiro Hayashi
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Publication number: 20200321239Abstract: A semiconductor device is provided in which a zener diode having a desired breakdown voltage and a capacitor in which voltage dependence of capacitance is reduced are mounted together, and various circuits are realized. The semiconductor device includes: a semiconductor layer; a first conductivity type well that is arranged in a first region of the semiconductor layer; a first conductivity type first impurity diffusion region that is arranged in the well; a first conductivity type second impurity diffusion region that is arranged in a second region of the semiconductor layer; an insulating film that is arranged on the second impurity diffusion region; an electrode that is arranged on the insulating film; and a second conductivity type third impurity diffusion region that is arranged at least on the first impurity diffusion region.Type: ApplicationFiled: June 19, 2020Publication date: October 8, 2020Applicant: SEIKO EPSON CORPORATIONInventors: Kazunobu KUWAZAWA, Shigeyuki SAKUMA, Hiroaki NITTA, Mitsuo SEKISAWA, Takehiro ENDO
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Publication number: 20200295746Abstract: Provided is a drive control device including: a first output node coupled to a gate node of a high-side transistor; a second output node coupled to a drive node; a first transistor provided between a first power supply node and the first output node; and a current limiting circuit and a second transistor provided in series between the first output node and the second output node, in which the current limiting circuit limits a current from the drive node toward the first output node to a predetermined value. The current limiting circuit is, for example, a transistor having a direction opposite to that of the second transistor.Type: ApplicationFiled: March 10, 2020Publication date: September 17, 2020Applicant: SEIKO EPSON CORPORATIONInventors: Toshimichi YAMADA, Tatsuro SHINMITSU, Kazuhiko OKAWA, Hiroaki NITTA, Masahiro HAYASHI
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Patent number: 10714375Abstract: A semiconductor device is provided in which a zener diode having a desired breakdown voltage and a capacitor in which voltage dependence of capacitance is reduced are mounted together, and various circuits are realized. The semiconductor device includes: a semiconductor layer; a first conductivity type well that is arranged in a first region of the semiconductor layer; a first conductivity type first impurity diffusion region that is arranged in the well; a first conductivity type second impurity diffusion region that is arranged in a second region of the semiconductor layer; an insulating film that is arranged on the second impurity diffusion region; an electrode that is arranged on the insulating film; and a second conductivity type third impurity diffusion region that is arranged at least on the first impurity diffusion region.Type: GrantFiled: November 30, 2016Date of Patent: July 14, 2020Assignee: SEIKO EPSON CORPORATIONInventors: Kazunobu Kuwazawa, Shigeyuki Sakuma, Hiroaki Nitta, Mitsuo Sekisawa, Takehiro Endo
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Patent number: 10588444Abstract: A heating cooker of the invention includes a blade rotating in first and second rotation directions around a rotation axle in the cooking container to stir a heating-target object put in the cooking container, the blade including a first functional portion pressing the heating-target object toward a side wall of the cooking container when rotating in the first rotation direction, and a second functional portion pressing the heating-target object not toward the side wall of the cooking container when rotating in the second rotation direction.Type: GrantFiled: April 3, 2014Date of Patent: March 17, 2020Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Taku Kiriishi, Katsuyuki Ohta, Hiroaki Nitta
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Patent number: 10541299Abstract: A semiconductor device includes a first conductivity type semiconductor substrate, a second conductivity type first and second buried diffusion layers that are arranged in the semiconductor substrate, a semiconductor layer arranged on the semiconductor substrate, a second conductivity type first impurity diffusion region that is arranged in the semiconductor layer, a second conductivity type second impurity diffusion region that is arranged, in the semiconductor layer, on the second buried diffusion layer, a second conductivity type first well that is arranged in a first region of the semiconductor layer, a first conductivity type second well that is arranged, in the semiconductor layer, in a second region, a first conductivity type third and fourth impurity diffusion regions that are arranged in the first well, and a first conductivity type fifth impurity diffusion region that is arranged in the second well.Type: GrantFiled: November 30, 2016Date of Patent: January 21, 2020Assignee: SEIKO EPSON CORPORATIONInventors: Kazunobu Kuwazawa, Shigeyuki Sakuma, Hiroaki Nitta, Mitsuo Sekisawa, Takehiro Endo
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Patent number: 10271559Abstract: Smoking device includes smoking chamber, smoke generating chamber, smoking heater, communication path, and fan. Smoking chamber houses raw material of a smoked food product. Smoke generating chamber is disposed below smoking chamber. Smoking heater generates smoke in smoke generating chamber by heating smoking material housed in smoke generating chamber. Communication path communicates smoking chamber with smoke generating chamber. Cooling fan cools smoke passing through communication path. According to the present aspect, a desired smoked product can be manufactured by using a sufficient amount of smoke at any smoking temperature.Type: GrantFiled: July 12, 2016Date of Patent: April 30, 2019Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Hiroaki Nitta, Taku Kiriishi
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Publication number: 20190069558Abstract: The automatic bread maker has case 23 for accommodating bread-making material, heater for heating case, and temperature detector for detecting the temperature of case. The automatic bread maker further has pulverizing and mixing section and controller. Pulverizing/mixing section is disposed on bottom of case. While rotating, it pulverizes and mixes the material in case. Controller controls heater and pulverizing and mixing section according to the temperature of case. Controller governs a pulverizing step for producing rice paste from the material and a mixing step for mixing the rice paste after the pulverizing step. In the pulverizing step, pulverizing and mixing section rotates in a rotation speed range the same as that in the mixing step. The structure suppresses friction heat produced in pulverizing rice grains. This suppresses gelatinization of rice starch, providing rice paste with stable viscosity.Type: ApplicationFiled: February 28, 2017Publication date: March 7, 2019Inventors: Hiroaki NITTA, Kyoko IDA
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Publication number: 20180325132Abstract: Smoking device includes smoking chamber, smoke generating chamber, smoking heater, communication path, and fan. Smoking chamber houses raw material of a smoked food product. Smoke generating chamber is disposed below smoking chamber. Smoking heater generates smoke in smoke generating chamber by heating smoking material housed in smoke generating chamber. Communication path communicates smoking chamber with smoke generating chamber. Cooling fan cools smoke passing through communication path. According to the present aspect, a desired smoked product can be manufactured by using a sufficient amount of smoke at any smoking temperature.Type: ApplicationFiled: July 12, 2016Publication date: November 15, 2018Inventors: Hiroaki NITTA, Taku KIRIISHI
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Patent number: 9911814Abstract: A semiconductor device includes a P-type semiconductor substrate, a plurality of N-type buried diffusion layers that are arranged in the semiconductor substrate, an N-type first semiconductor layer that is arranged in a first region on a first buried diffusion layer, an N-type second semiconductor layer that is arranged in a second region on a second buried diffusion layer, an N-type first impurity diffusion region that surrounds the first region in plan view, a P-type second impurity diffusion region that is arranged in the second semiconductor layer, an N-type third impurity diffusion region that is arranged in the second semiconductor layer, an N-type fourth impurity diffusion region that is arranged in the first semiconductor layer. The second region is a region in which an N-type impurity diffusion region that has a higher impurity concentration than the second semiconductor layer cannot be arranged.Type: GrantFiled: December 5, 2016Date of Patent: March 6, 2018Assignee: SEIKO EPSON CORPORATIONInventors: Hiroaki Nitta, Kazunobu Kuwazawa
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Patent number: 9786616Abstract: A semiconductor apparatus includes elements formed on a substrate, a first insulation layer, a first pad and a second pad arranged on the first insulation layer and located above the elements, and a second insulation layer that is arranged on the side surfaces and upper surfaces of the first pad and the second pad. The second insulation layer includes openings at upper surfaces of the first pad and the second pad. The thickness of the first pad and the second pad is 2 ?m or more, the thickness of the second insulation layer is less than or equal to ? of the thickness of the first pad and the second pad, and the distance between the first pad and the second pad is greater than or equal to four times the thickness of the first pad and the second pad.Type: GrantFiled: August 8, 2016Date of Patent: October 10, 2017Assignee: SEIKO EPSON CORPORATIONInventors: Kazunobu Kuwazawa, Hiroaki Nitta, Takehiro Endo, Mitsuo Sekisawa
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Publication number: 20170179239Abstract: A semiconductor device includes a P-type semiconductor substrate, a plurality of N-type buried diffusion layers that are arranged in the semiconductor substrate, an N-type first semiconductor layer that is arranged in a first region on a first buried diffusion layer, an N-type second semiconductor layer that is arranged in a second region on a second buried diffusion layer, an N-type first impurity diffusion region that surrounds the first region in plan view, a P-type second impurity diffusion region that is arranged in the second semiconductor layer, an N-type third impurity diffusion region that is arranged in the second semiconductor layer, an N-type fourth impurity diffusion region that is arranged in the first semiconductor layer. The second region is a region in which an N-type impurity diffusion region that has a higher impurity concentration than the second semiconductor layer cannot be arranged.Type: ApplicationFiled: December 5, 2016Publication date: June 22, 2017Applicant: SEIKO EPSON CORPORATIONInventors: Hiroaki NITTA, Kazunobu KUWAZAWA
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Publication number: 20170170053Abstract: A semiconductor device is provided in which a zener diode having a desired breakdown voltage and a capacitor in which voltage dependence of capacitance is reduced are mounted together, and various circuits are realized. The semiconductor device includes: a semiconductor layer; a first conductivity type well that is arranged in a first region of the semiconductor layer; a first conductivity type first impurity diffusion region that is arranged in the well; a first conductivity type second impurity diffusion region that is arranged in a second region of the semiconductor layer; an insulating film that is arranged on the second impurity diffusion region; an electrode that is arranged on the insulating film; and a second conductivity type third impurity diffusion region that is arranged at least on the first impurity diffusion region.Type: ApplicationFiled: November 30, 2016Publication date: June 15, 2017Applicant: SEIKO EPSON CORPORATIONInventors: Kazunobu KUWAZAWA, Shigeyuki SAKUMA, Hiroaki NITTA, Mitsuo SEKISAWA, Takehiro ENDO
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Publication number: 20170170262Abstract: A semiconductor device includes a first conductivity type semiconductor substrate, a second conductivity type first and second buried diffusion layers that are arranged in the semiconductor substrate, a semiconductor layer arranged on the semiconductor substrate, a second conductivity type first impurity diffusion region that is arranged in the semiconductor layer, a second conductivity type second impurity diffusion region that is arranged, in the semiconductor layer, on the second buried diffusion layer, a second conductivity type first well that is arranged in a first region of the semiconductor layer, a first conductivity type second well that is arranged, in the semiconductor layer, in a second region, a first conductivity type third and fourth impurity diffusion regions that are arranged in the first well, and a first conductivity type fifth impurity diffusion region that is arranged in the second well.Type: ApplicationFiled: November 30, 2016Publication date: June 15, 2017Applicant: SEIKO EPSON CORPORATIONInventors: Kazunobu KUWAZAWA, Shigeyuki SAKUMA, Hiroaki NITTA, Mitsuo SEKISAWA, Takehiro ENDO
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Publication number: 20170053880Abstract: A semiconductor apparatus includes elements formed on a substrate, a first insulation layer, a first pad and a second pad arranged on the first insulation layer and located above the elements, and a second insulation layer that is arranged on the side surfaces and upper surfaces of the first pad and the second pad. The second insulation layer includes openings at upper surfaces of the first pad and the second pad. The thickness of the first pad and the second pad is 2 ?m or more, the thickness of the second insulation layer is less than or equal to ? of the thickness of the first pad and the second pad, and the distance between the first pad and the second pad is greater than or equal to four times the thickness of the first pad and the second pad.Type: ApplicationFiled: August 8, 2016Publication date: February 23, 2017Applicant: SEIKO EPSON CORPORATIONInventors: Kazunobu KUWAZAWA, Hiroaki NITTA, Takehiro ENDO, Mitsuo SEKISAWA
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Patent number: 9425197Abstract: A semiconductor device includes a P-channel DMOS transistor provided with an N-type gate electrode, a P-channel MOS transistor provided with a P-type gate electrode, and an N-channel MOS transistor provided with an N-type gate electrode. The N-type gate electrode of the P-channel DMOS transistor desirably has a first end portion that is located on a source side of the P-channel DMOS transistor, a second end portion that is located on a drain side of the P-channel DMOS transistor, and a P-type diffusion layer at the first end portion.Type: GrantFiled: March 26, 2015Date of Patent: August 23, 2016Assignee: SEIKO EPSON CORPORATIONInventors: Hiroaki Nitta, Hideyuki Akanuma, Kazunobu Kuwazawa