Patents by Inventor Hiroaki Nitta

Hiroaki Nitta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10958263
    Abstract: Provided is a drive control device including: a first output node coupled to a gate node of a high-side transistor; a second output node coupled to a drive node; a first transistor provided between a first power supply node and the first output node; and a current limiting circuit and a second transistor provided in series between the first output node and the second output node, in which the current limiting circuit limits a current from the drive node toward the first output node to a predetermined value. The current limiting circuit is, for example, a transistor having a direction opposite to that of the second transistor.
    Type: Grant
    Filed: March 10, 2020
    Date of Patent: March 23, 2021
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Toshimichi Yamada, Tatsuro Shinmitsu, Kazuhiko Okawa, Hiroaki Nitta, Masahiro Hayashi
  • Publication number: 20200321239
    Abstract: A semiconductor device is provided in which a zener diode having a desired breakdown voltage and a capacitor in which voltage dependence of capacitance is reduced are mounted together, and various circuits are realized. The semiconductor device includes: a semiconductor layer; a first conductivity type well that is arranged in a first region of the semiconductor layer; a first conductivity type first impurity diffusion region that is arranged in the well; a first conductivity type second impurity diffusion region that is arranged in a second region of the semiconductor layer; an insulating film that is arranged on the second impurity diffusion region; an electrode that is arranged on the insulating film; and a second conductivity type third impurity diffusion region that is arranged at least on the first impurity diffusion region.
    Type: Application
    Filed: June 19, 2020
    Publication date: October 8, 2020
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Kazunobu KUWAZAWA, Shigeyuki SAKUMA, Hiroaki NITTA, Mitsuo SEKISAWA, Takehiro ENDO
  • Publication number: 20200295746
    Abstract: Provided is a drive control device including: a first output node coupled to a gate node of a high-side transistor; a second output node coupled to a drive node; a first transistor provided between a first power supply node and the first output node; and a current limiting circuit and a second transistor provided in series between the first output node and the second output node, in which the current limiting circuit limits a current from the drive node toward the first output node to a predetermined value. The current limiting circuit is, for example, a transistor having a direction opposite to that of the second transistor.
    Type: Application
    Filed: March 10, 2020
    Publication date: September 17, 2020
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Toshimichi YAMADA, Tatsuro SHINMITSU, Kazuhiko OKAWA, Hiroaki NITTA, Masahiro HAYASHI
  • Patent number: 10714375
    Abstract: A semiconductor device is provided in which a zener diode having a desired breakdown voltage and a capacitor in which voltage dependence of capacitance is reduced are mounted together, and various circuits are realized. The semiconductor device includes: a semiconductor layer; a first conductivity type well that is arranged in a first region of the semiconductor layer; a first conductivity type first impurity diffusion region that is arranged in the well; a first conductivity type second impurity diffusion region that is arranged in a second region of the semiconductor layer; an insulating film that is arranged on the second impurity diffusion region; an electrode that is arranged on the insulating film; and a second conductivity type third impurity diffusion region that is arranged at least on the first impurity diffusion region.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: July 14, 2020
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Kazunobu Kuwazawa, Shigeyuki Sakuma, Hiroaki Nitta, Mitsuo Sekisawa, Takehiro Endo
  • Patent number: 10588444
    Abstract: A heating cooker of the invention includes a blade rotating in first and second rotation directions around a rotation axle in the cooking container to stir a heating-target object put in the cooking container, the blade including a first functional portion pressing the heating-target object toward a side wall of the cooking container when rotating in the first rotation direction, and a second functional portion pressing the heating-target object not toward the side wall of the cooking container when rotating in the second rotation direction.
    Type: Grant
    Filed: April 3, 2014
    Date of Patent: March 17, 2020
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Taku Kiriishi, Katsuyuki Ohta, Hiroaki Nitta
  • Patent number: 10541299
    Abstract: A semiconductor device includes a first conductivity type semiconductor substrate, a second conductivity type first and second buried diffusion layers that are arranged in the semiconductor substrate, a semiconductor layer arranged on the semiconductor substrate, a second conductivity type first impurity diffusion region that is arranged in the semiconductor layer, a second conductivity type second impurity diffusion region that is arranged, in the semiconductor layer, on the second buried diffusion layer, a second conductivity type first well that is arranged in a first region of the semiconductor layer, a first conductivity type second well that is arranged, in the semiconductor layer, in a second region, a first conductivity type third and fourth impurity diffusion regions that are arranged in the first well, and a first conductivity type fifth impurity diffusion region that is arranged in the second well.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: January 21, 2020
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Kazunobu Kuwazawa, Shigeyuki Sakuma, Hiroaki Nitta, Mitsuo Sekisawa, Takehiro Endo
  • Patent number: 10271559
    Abstract: Smoking device includes smoking chamber, smoke generating chamber, smoking heater, communication path, and fan. Smoking chamber houses raw material of a smoked food product. Smoke generating chamber is disposed below smoking chamber. Smoking heater generates smoke in smoke generating chamber by heating smoking material housed in smoke generating chamber. Communication path communicates smoking chamber with smoke generating chamber. Cooling fan cools smoke passing through communication path. According to the present aspect, a desired smoked product can be manufactured by using a sufficient amount of smoke at any smoking temperature.
    Type: Grant
    Filed: July 12, 2016
    Date of Patent: April 30, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Hiroaki Nitta, Taku Kiriishi
  • Publication number: 20190069558
    Abstract: The automatic bread maker has case 23 for accommodating bread-making material, heater for heating case, and temperature detector for detecting the temperature of case. The automatic bread maker further has pulverizing and mixing section and controller. Pulverizing/mixing section is disposed on bottom of case. While rotating, it pulverizes and mixes the material in case. Controller controls heater and pulverizing and mixing section according to the temperature of case. Controller governs a pulverizing step for producing rice paste from the material and a mixing step for mixing the rice paste after the pulverizing step. In the pulverizing step, pulverizing and mixing section rotates in a rotation speed range the same as that in the mixing step. The structure suppresses friction heat produced in pulverizing rice grains. This suppresses gelatinization of rice starch, providing rice paste with stable viscosity.
    Type: Application
    Filed: February 28, 2017
    Publication date: March 7, 2019
    Inventors: Hiroaki NITTA, Kyoko IDA
  • Publication number: 20180325132
    Abstract: Smoking device includes smoking chamber, smoke generating chamber, smoking heater, communication path, and fan. Smoking chamber houses raw material of a smoked food product. Smoke generating chamber is disposed below smoking chamber. Smoking heater generates smoke in smoke generating chamber by heating smoking material housed in smoke generating chamber. Communication path communicates smoking chamber with smoke generating chamber. Cooling fan cools smoke passing through communication path. According to the present aspect, a desired smoked product can be manufactured by using a sufficient amount of smoke at any smoking temperature.
    Type: Application
    Filed: July 12, 2016
    Publication date: November 15, 2018
    Inventors: Hiroaki NITTA, Taku KIRIISHI
  • Patent number: 9911814
    Abstract: A semiconductor device includes a P-type semiconductor substrate, a plurality of N-type buried diffusion layers that are arranged in the semiconductor substrate, an N-type first semiconductor layer that is arranged in a first region on a first buried diffusion layer, an N-type second semiconductor layer that is arranged in a second region on a second buried diffusion layer, an N-type first impurity diffusion region that surrounds the first region in plan view, a P-type second impurity diffusion region that is arranged in the second semiconductor layer, an N-type third impurity diffusion region that is arranged in the second semiconductor layer, an N-type fourth impurity diffusion region that is arranged in the first semiconductor layer. The second region is a region in which an N-type impurity diffusion region that has a higher impurity concentration than the second semiconductor layer cannot be arranged.
    Type: Grant
    Filed: December 5, 2016
    Date of Patent: March 6, 2018
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Hiroaki Nitta, Kazunobu Kuwazawa
  • Patent number: 9786616
    Abstract: A semiconductor apparatus includes elements formed on a substrate, a first insulation layer, a first pad and a second pad arranged on the first insulation layer and located above the elements, and a second insulation layer that is arranged on the side surfaces and upper surfaces of the first pad and the second pad. The second insulation layer includes openings at upper surfaces of the first pad and the second pad. The thickness of the first pad and the second pad is 2 ?m or more, the thickness of the second insulation layer is less than or equal to ? of the thickness of the first pad and the second pad, and the distance between the first pad and the second pad is greater than or equal to four times the thickness of the first pad and the second pad.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: October 10, 2017
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Kazunobu Kuwazawa, Hiroaki Nitta, Takehiro Endo, Mitsuo Sekisawa
  • Publication number: 20170179239
    Abstract: A semiconductor device includes a P-type semiconductor substrate, a plurality of N-type buried diffusion layers that are arranged in the semiconductor substrate, an N-type first semiconductor layer that is arranged in a first region on a first buried diffusion layer, an N-type second semiconductor layer that is arranged in a second region on a second buried diffusion layer, an N-type first impurity diffusion region that surrounds the first region in plan view, a P-type second impurity diffusion region that is arranged in the second semiconductor layer, an N-type third impurity diffusion region that is arranged in the second semiconductor layer, an N-type fourth impurity diffusion region that is arranged in the first semiconductor layer. The second region is a region in which an N-type impurity diffusion region that has a higher impurity concentration than the second semiconductor layer cannot be arranged.
    Type: Application
    Filed: December 5, 2016
    Publication date: June 22, 2017
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Hiroaki NITTA, Kazunobu KUWAZAWA
  • Publication number: 20170170262
    Abstract: A semiconductor device includes a first conductivity type semiconductor substrate, a second conductivity type first and second buried diffusion layers that are arranged in the semiconductor substrate, a semiconductor layer arranged on the semiconductor substrate, a second conductivity type first impurity diffusion region that is arranged in the semiconductor layer, a second conductivity type second impurity diffusion region that is arranged, in the semiconductor layer, on the second buried diffusion layer, a second conductivity type first well that is arranged in a first region of the semiconductor layer, a first conductivity type second well that is arranged, in the semiconductor layer, in a second region, a first conductivity type third and fourth impurity diffusion regions that are arranged in the first well, and a first conductivity type fifth impurity diffusion region that is arranged in the second well.
    Type: Application
    Filed: November 30, 2016
    Publication date: June 15, 2017
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Kazunobu KUWAZAWA, Shigeyuki SAKUMA, Hiroaki NITTA, Mitsuo SEKISAWA, Takehiro ENDO
  • Publication number: 20170170053
    Abstract: A semiconductor device is provided in which a zener diode having a desired breakdown voltage and a capacitor in which voltage dependence of capacitance is reduced are mounted together, and various circuits are realized. The semiconductor device includes: a semiconductor layer; a first conductivity type well that is arranged in a first region of the semiconductor layer; a first conductivity type first impurity diffusion region that is arranged in the well; a first conductivity type second impurity diffusion region that is arranged in a second region of the semiconductor layer; an insulating film that is arranged on the second impurity diffusion region; an electrode that is arranged on the insulating film; and a second conductivity type third impurity diffusion region that is arranged at least on the first impurity diffusion region.
    Type: Application
    Filed: November 30, 2016
    Publication date: June 15, 2017
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Kazunobu KUWAZAWA, Shigeyuki SAKUMA, Hiroaki NITTA, Mitsuo SEKISAWA, Takehiro ENDO
  • Publication number: 20170053880
    Abstract: A semiconductor apparatus includes elements formed on a substrate, a first insulation layer, a first pad and a second pad arranged on the first insulation layer and located above the elements, and a second insulation layer that is arranged on the side surfaces and upper surfaces of the first pad and the second pad. The second insulation layer includes openings at upper surfaces of the first pad and the second pad. The thickness of the first pad and the second pad is 2 ?m or more, the thickness of the second insulation layer is less than or equal to ? of the thickness of the first pad and the second pad, and the distance between the first pad and the second pad is greater than or equal to four times the thickness of the first pad and the second pad.
    Type: Application
    Filed: August 8, 2016
    Publication date: February 23, 2017
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Kazunobu KUWAZAWA, Hiroaki NITTA, Takehiro ENDO, Mitsuo SEKISAWA
  • Patent number: 9425197
    Abstract: A semiconductor device includes a P-channel DMOS transistor provided with an N-type gate electrode, a P-channel MOS transistor provided with a P-type gate electrode, and an N-channel MOS transistor provided with an N-type gate electrode. The N-type gate electrode of the P-channel DMOS transistor desirably has a first end portion that is located on a source side of the P-channel DMOS transistor, a second end portion that is located on a drain side of the P-channel DMOS transistor, and a P-type diffusion layer at the first end portion.
    Type: Grant
    Filed: March 26, 2015
    Date of Patent: August 23, 2016
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Hiroaki Nitta, Hideyuki Akanuma, Kazunobu Kuwazawa
  • Publication number: 20160073814
    Abstract: A heating cooker of the invention includes a blade rotating in first and second rotation directions around a rotation axle in the cooking container to stir a heating-target object put in the cooking container, the blade including a first functional portion pressing the heating-target object toward a side wall of the cooking container when rotating in the first rotation direction, and a second functional portion pressing the heating-target object not toward the side wall of the cooking container when rotating in the second rotation direction.
    Type: Application
    Filed: April 3, 2014
    Publication date: March 17, 2016
    Inventors: Taku KIRIISHI, Katsuyuki OHTA, Hiroaki NITTA
  • Publication number: 20150287726
    Abstract: A semiconductor device includes a P-channel DMOS transistor provided with an N-type gate electrode, a P-channel MOS transistor provided with a P-type gate electrode, and an N-channel MOS transistor provided with an N-type gate electrode. The N-type gate electrode of the P-channel DMOS transistor desirably has a first end portion that is located on a source side of the P-channel DMOS transistor, a second end portion that is located on a drain side of the P-channel DMOS transistor, and a P-type diffusion layer at the first end portion.
    Type: Application
    Filed: March 26, 2015
    Publication date: October 8, 2015
    Inventors: Hiroaki NITTA, Hideyuki AKANUMA, Kazunobu KUWAZAWA
  • Patent number: 8481270
    Abstract: The present invention provides a method and kit for detection of two or more target molecules in a single tissue sample, such as for gene and protein dual detection in a single tissue sample. Methods comprise treating a tissue sample with a first binding moiety that specifically binds a first target molecule. Methods further comprise treating the tissue sample with a solution containing a soluble electron-rich aromatic compound prior to or concomitantly with contacting the tissue sample with a hapten-labeled binding moiety and detecting a second target molecule. In one example, the first target molecule is a protein and the second is a nucleic acid sequence, the first target molecule being detected by immunohistochemistry and the second by in situ hybridization. The disclosed method reduces background due to non-specific binding of the hapten-labeled specific binding moiety to an insoluble electron rich compound deposited near the first target molecule.
    Type: Grant
    Filed: August 21, 2009
    Date of Patent: July 9, 2013
    Assignee: Ventana Medical Systems, Inc.
    Inventors: Richard Gniewek, Michael Farrell, Hiroaki Nitta, Megan Lehrkamp, Jerome Kosmeder, Brian Daniel Kelly, Thomas Grogan, Fabien Gaire, Mary Padilla, Christopher Bieniarz
  • Patent number: 8330219
    Abstract: A semiconductor device includes: a semiconductor substrate having a first conductivity type; a well having a second conductivity type and provided inside the semiconductor substrate; a first impurity region having the first conductivity type and provided within the well; a second impurity region having the second conductivity type, provided inside the well and away from the first impurity region; and a third impurity region having a first conductivity type, provided surrounding the well and away from the second impurity region. In this semiconductor device, the well is formed to be deeper than the first impurity region, the second impurity region, and the third impurity region, in a thickness direction of the semiconductor substrate; and a minimum distance between the first impurity region and the second impurity region is smaller than a minimum distance between the second impurity region and the third impurity region.
    Type: Grant
    Filed: June 25, 2009
    Date of Patent: December 11, 2012
    Assignee: Seiko Epson Corporation
    Inventors: Tomoyuki Furuhata, Hideyuki Akanuma, Hiroaki Nitta