Patents by Inventor Hiroaki Sudo

Hiroaki Sudo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040071078
    Abstract: The degree of multiplexing of a code division multiplexed signal transmitted by subcarriers is selected on a subcarrier-by-subcarrier basis. As a result, inter-code interference on the propagation path and degradation on the propagation path are lower for a code division multiplexed signal allocated to subcarriers with a low degree of signal multiplexing (G1) than for transmit signals allocated to subcarriers with a high degree of multiplexing. By this means, it is possible to prevent degradation of the error rate characteristics of important information without lowering spectral efficiency significantly as compared with the case in which the degree of signal multiplexing is decided uniformly for all subcarriers, and to achieve compatibility between spectral efficiency and error rate characteristics.
    Type: Application
    Filed: July 21, 2003
    Publication date: April 15, 2004
    Inventor: Hiroaki Sudo
  • Patent number: 6714511
    Abstract: The subtractor of the reception system calculates the channel quality using an optimal guard interval length detection signal inserted into one carrier by the transmission system, then the optimal guard interval length detector calculates the minimum guard interval length necessary to eliminate delayed signals using this calculated channel quality, inserts the control signal indicating this guard interval length into one carrier and the reception system sets the guard interval length using this control signal.
    Type: Grant
    Filed: December 16, 1999
    Date of Patent: March 30, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hiroaki Sudo, Mitsuru Uesugi
  • Publication number: 20040028007
    Abstract: The transmitting side is equipped with chip steering section 30 that performs a chip steering that shifts the allocation of N×M chip elements upon their respective subcarriers by one chip for every transmission unit in sequence, and the receiving side is equipped with a parallel/serial conversion section and an inverse chip steering section that rearranges the allocation of the chip elements shifted in chip steering section 30 back to original.
    Type: Application
    Filed: June 16, 2003
    Publication date: February 12, 2004
    Inventors: Atsushi Sumasu, Hiroaki Sudo
  • Patent number: 6671524
    Abstract: Level detectors 305 to 312 detect reception levels of uplink bursts received by their respective subcarriers/branches, then interpolation sections 313 to 320 estimate reception levels of the next uplink burst from the reception levels of a plurality of uplink bursts detected, select the branch with the maximum estimated value for each subcarrier and sends each subcarrier of the next downlink burst to be transmitted using this selected branch.
    Type: Grant
    Filed: December 9, 1999
    Date of Patent: December 30, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Hiroaki Sudo
  • Patent number: 6647025
    Abstract: Multiplier 103 calculates the correlation value of the received signal with the one-symbol-delayed received signal, integrator 104 integrates the calculated correlation value, subtracter 105 executes subtract processing between the integrated value and an arbitrary threshold level, and decider 106 decides a level of the resultant, fastest timing detection section 107 compares the peak detected timing for each of a plurality of frames received during a predetermined time to each other to select the fastest peak detected timing, and using the selected timing as a processing initiation timing, FFT circuit 108 executes FFT processing on the received signal.
    Type: Grant
    Filed: November 23, 1999
    Date of Patent: November 11, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Hiroaki Sudo
  • Publication number: 20030189917
    Abstract: A base station (10) performs bi-directional radio communications with terminal station apparatuses using communication frames each having time slots and being composed of a first region with a predetermined open-loop period and a second region with an open-loop period shorter than the open-loop period of the first region. A level detecting section (21) detects a received level of an uplink slot configured in the second region. A transmission diversity section (14) performs diversity transmission on a downlink transmission signal assigned to a downlink slot corresponding to the uplink slot, corresponding to a result of detection of the received level. It is thereby possible to enhance the effect of improving the received quality due to transmission diversity without degrading the transmission efficiency.
    Type: Application
    Filed: December 18, 2002
    Publication date: October 9, 2003
    Inventor: Hiroaki Sudo
  • Publication number: 20030179776
    Abstract: The pilot signal generation section 103 generates pilot signals in such a way that the pilot signals have a predetermined time-varying pattern on pilot carriers. The pilot signal insertion section 104 allows the pilot carriers to carry only pilot signals. The apparatus on the receiving side carries out channel estimation by correlating the plurality of pilot signals carried on the pilot carriers with the same pattern as that used on the transmitting side. Furthermore, the apparatus on the transmitting side sends pilot signals having a time-varying pattern carried on subcarriers involving DC components which would not be used for information transmission by conventional multicarriers. This makes it possible to improve the transmission efficiency in a radio communication based on a multicarrier modulation system.
    Type: Application
    Filed: February 10, 2003
    Publication date: September 25, 2003
    Inventors: Atsushi Sumasu, Hiroaki Sudo, Kenichi Miyoshi
  • Patent number: 6625111
    Abstract: The known signal that is transmission data for the pilot carrier is output to multiplier 103 to be subjected to amplitude adjustment (gain control) using a predetermined coefficient. The coefficient is set as appropriate in the range that makes an amplitude of the known signal larger than the amplitude of a message signal in consideration of, for example, error rate deterioration and increment of peak power in the entire transmission power. In addition, since the number of pilot carriers is small as compared to the number of all carriers, the increment of the gain of the pilot carrier does not generally have a large effect on the increment of the peak power.
    Type: Grant
    Filed: March 6, 2000
    Date of Patent: September 23, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Hiroaki Sudo
  • Patent number: 6584305
    Abstract: A radio receiving system includes an orthogonally-modulated waveform detection/channel filter section 4, an I signal root Nyquist filter 20, a Q signal root Nyquist filter 21, and a signal detection/demodulation section 25. The orthogonally-modulated waveform detection/channel filter section 4 further includes a first filter (a band pass filter) 2 which permits passage of only a signal at a frequency band assigned to a communications system from which the radio receiving system receives a signal; a sample-and-hold circuit 5; a Hilbert transformer 6; a first channel filter 7 through N-th channel filter 9; and a clock signal shaping/controlling section 15. The band pass filter 2 is provided with the characteristics which cancel the aperture effect due to a sampling operation, thus compensating for the aperture effect due to a sampling operation.
    Type: Grant
    Filed: May 11, 1998
    Date of Patent: June 24, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Gen-ichiro Ohta, Kazunori Inogai, Hiroaki Sudo, Fujio Sasaki
  • Patent number: 6584092
    Abstract: Delay circuits 409 and 410 delay a digital baseband signal received by one symbol. Complex multiplier 411 performs a complex multiplication using the received digital baseband signal and the signal delayed by delay circuits 409 and 410. Of the multiplication result of complex multiplier 411, second accumulator 412 outputs the value resulting from an accumulation of the multiplication result of the phase reference symbol in the received digital baseband signal and that of the last half of the synchronization symbol in the delayed signal to frequency offset detector 413.
    Type: Grant
    Filed: November 4, 1999
    Date of Patent: June 24, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Hiroaki Sudo
  • Publication number: 20030058976
    Abstract: A radio receiving system, which receives an input signal in a direct conversion receiving mode through the use of a plurality of cascaded channel filters, each including a complex coefficient filter, to obtain a desired waveform, wherein a center frequency of a preliminary channel filter corresponds more closely with the frequency of the desired waveform than a center frequency of a subsequent channel filter.
    Type: Application
    Filed: October 23, 2002
    Publication date: March 27, 2003
    Inventors: Gen-Ichiro Ohta, Kazunori Inogai, Hiroaki Sudo, Fujio Sasaki
  • Publication number: 20030031121
    Abstract: By providing determining section that determine a number of known signals for transmission path estimation to be inserted in a transmit signal based on channel quality with respect to a communicating party, and generating section that perform inverse Fourier transform processing on an information signal and the number of known signals for transmission path estimation determined by the determining section and generating a transmit signal for the communicating party, it is possible to realize an OFDM communication apparatus that can achieve both an improvement in demodulated signal error rate characteristics and an improvement in information signal transmission efficiency.
    Type: Application
    Filed: July 9, 2002
    Publication date: February 13, 2003
    Inventor: Hiroaki Sudo
  • Publication number: 20030012126
    Abstract: An OFDM communication apparatus and OFDM communication method that both improve information signal transmission efficiency and improve demodulated signal error rate characteristics in an OFDM method to which multicasting is applied. An OFDM communication apparatus according to the present invention comprises a receiving section that receives an OFDM signal transmitted to a plurality of OFDM communication apparatuses, a detecting section that detects whether or not there is an error in a received OFDM signal, a generating section that generates a retransmission request OFDM signal by superimposing a retransmission request signal on a previously specified subcarrier when there is an error in a received OFDM signal, and a transmitting section that transmits a generated retransmission request OFDM signal at previously set timing common to all the above-mentioned plurality of OFDM communication apparatuses.
    Type: Application
    Filed: July 25, 2002
    Publication date: January 16, 2003
    Inventor: Hiroaki Sudo
  • Publication number: 20020181610
    Abstract: OFDM modulation of a transmission data is performed in an IDFT section 103 to generate an OFDM signal; it is determined whether a multicarrier signal generated in a peak detecting circuit 106 is required to be suppressed; the multicarrier signal which is determined to be required for suppression is equally suppressed in an equally-suppressing circuit 107; and peak voltage is suppressed by clipping a peak voltage part in a clipping circuit 108.
    Type: Application
    Filed: April 26, 2002
    Publication date: December 5, 2002
    Inventors: Atsushi Sumasu, Hiroaki Sudo
  • Publication number: 20020150038
    Abstract: After digital modulation by digital modulation section 101, OFDM symbols (first OFDM symbol group) converted to parallel by S/P conversion section 102 are output to mapping section 103, where of a plurality of subcarriers on which the first OFDM symbol group is superimposed, the OFDM symbols superimposed on a predetermined number of subcarriers are set to “0” to expand thereby the OFDM symbol space. As many OFDM symbols as those of the first OFDM symbol group are selected in ascending order of peak power from among symbol patterns in this space, the first OFDM symbol group is associated with this selected OFDM symbol, this associated and selected OFDM symbol is output, this selected OFDM symbol is subjected to an inverse fast Fourier transform by IFFT section 104 and then transmitted.
    Type: Application
    Filed: March 7, 2002
    Publication date: October 17, 2002
    Inventors: Atsushi Sumasu, Osamu Kato, Mitsuru Uesugi, Toyoki Ue, Hiroaki Sudo, Kazunori Inogai
  • Patent number: 6456677
    Abstract: The synchronizing apparatus includes a block for detecting a code from an input signal, a block for detecting from the code the variable points of the code at several times as high as the symbol rate, a block for calculating a histogram of the detected variables of the code to time, and a block for deciding that the phase number at which the calculated histogram takes the maximum value is a symbol synchronization point. This synchronizing apparatus detects the zero-cross points of an intermediate frequency band signal at N times as high as the symbol rate. It also calculates a histogram of detected time (0 to N−1). The time (0 to N−1) at which the histogram is the maximum within a predetermined detected time is selected as a symbol clock, and thereby symbol synchronization is established.
    Type: Grant
    Filed: November 13, 2000
    Date of Patent: September 24, 2002
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Katsuhiko Hiramatsu, Mitsuru Uesugi, Hiroaki Sudo
  • Publication number: 20020027875
    Abstract: An average value of reception power of subcarriers A to D is calculated by a control circuit 162, and the average value is divided by envelops of received signals of subcarriers A to D, respectively, so as to calculate a coefficient signal of each subcarrier. Multipliers 106 to 109 multiply transmitting signals of subcarriers A to D output from mapping circuits 102 to 105 by the coefficient signals, respectively. Whereby, power between the subcarriers at a reception time can be maintained substantially constant so as to improve an error rate characteristic.
    Type: Application
    Filed: October 31, 2001
    Publication date: March 7, 2002
    Inventors: Hiroaki Sudo, Kimihiko Ishikawa
  • Patent number: 6345036
    Abstract: An average value of reception power of subcarriers A to D is calculated by a control circuit 162, and the average value is divided by envelops of received signals of subcarriers A to D, respectively, so as to calculate a coefficient signal of each subcarrier. Multipliers 106 to 109 multiply transmitting signals of subcarriers A to D output from mapping circuits 102 to 105 by the coefficient signals, respectively. Whereby, power between the subcarriers at a reception time can be maintained substantially constant so as to improve an error rate characteristic.
    Type: Grant
    Filed: June 29, 2000
    Date of Patent: February 5, 2002
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hiroaki Sudo, Kimihiko Ishikawa
  • Patent number: 6307897
    Abstract: A received signal obtained from an antenna is subjected to high-frequency amplification. The amplified signal is supplied to a first bandpass filter, which extracts only signals of all the channels of a communications system concerned while filtering out other radio signals. The extracted signals are frequency-converted by using a local oscillation frequency, and only a desired wave is passed by a second bandpass filter. The desired wave is supplied to a sample-and-hold circuit, which performs sampling according to the bandwidth-limiting sampling theorem. A resulting discrete signal is supplied to an I-axis-component and Q-axis-component separating circuits, where the polarity of sample values is inverted for every other clock pulse with respect to each of the I and Q axes to thereby effect Hilbert transform. Resulting two orthogonal components on a phase plane are supplied to a complex coefficient filter.
    Type: Grant
    Filed: December 8, 1999
    Date of Patent: October 23, 2001
    Assignee: Matsushita Electric Industiral Co., Ltd.
    Inventors: Gen-ichiro Ohta, Kazunori Inogai, Hiroaki Sudo, Fujio Sasaki
  • Patent number: 6208701
    Abstract: The synchronizing apparatus includes a block for detecting a code from an input signal, a block for detecting from the code the variable points of the code at several times as high as the symbol rate, a block for calculating a histogram of the detected variables of the code to time, and a block for deciding that the phase number at which the calculated histogram takes the maximum value is a symbol synchronization point. This synchronizing apparatus detects the zero-cross points of an intermediate frequency band signal at N times as high as the symbol rate. It also calculates a histogram of detected time (0 to N−1). The time (0 to N−1) at which the histogram is the maximum within a predetermined detected time is selected as a symbol clock, and thereby symbol synchronization is established.
    Type: Grant
    Filed: June 3, 1997
    Date of Patent: March 27, 2001
    Assignee: Matsushita Electrical Industrial Co., Ltd.
    Inventors: Katsuhiko Hiramatsu, Mitsuru Uesugi, Hiroaki Sudo