Abstract: A nitride semiconductor device includes: a first semiconductor layer made of first nitride semiconductor; a second semiconductor layer formed on a principal surface of the first semiconductor layer and made of second nitride semiconductor having a bandgap wider than that of the first nitride semiconductor; a control layer selectively formed on, or above, an upper portion of the second semiconductor layer and made of third nitride semiconductor having a p-type conductivity; source and drain electrodes formed on the second semiconductor layer at respective sides of the control layer; a gate electrode formed on the control layer; and a fourth semiconductor layer formed on a surface of the first semiconductor layer opposite to the principal surface, having a potential barrier in a valence band with respect to the first nitride semiconductor and made of fourth nitride semiconductor containing aluminum.

Abstract: According to an aspect of an embodiment, a storage apparatus has a storage for storing a plurality of compensation values in association with a plurality of bit sequence patterns, a head for writing data into a medium and a controller for controlling the apparatus and driving the head, the controller determining whether to use one of the compensation values to drive the head to write an instantaneous data bit in dependence upon the immediate preceding data bits in reference to the bit sequence patterns.

Abstract: A circuit device includes a substrate 11, and a transmission line 10. The transmission line 10 includes a dielectric film 13 formed on the substrate 11, and a signal line formed on the dielectric film 13. The dielectric film 13 includes a nano-composite film in which particles of a first material are dispersed in a second material.

Abstract: According to one embodiment, a write clock generator writes data to bits in a magnetic recording medium based on a write clock signal with a phase obtained by delaying the phase of a reference write clock signal. The write clock generator detects the amplitude of a read signal for the written data. The write clock generator repeats these operations with a phase delay varied. The write clock generator decides an optimum phase delay based on the amplitude detected for each phase delay.

Abstract: A semiconductor device includes: a first group-III nitride semiconductor layer formed on a substrate; a second group-III nitride semiconductor layer made of a single layer or two or more layers, formed on the first group-III nitride semiconductor layer, and acting as a barrier layer; a source electrode, a drain electrode, and a gate electrode formed on the second group-III nitride semiconductor layer, the gate electrode controlling a current flowing between the source and drain electrodes; and a heat radiation film with high thermal conductivity which covers, as a surface passivation film, the entire surface other than a bonding pad.

Abstract: According to one embodiment, a signal reproducing circuit reproduces a signal read from a recording medium on which the signal has been recorded by perpendicular magnetic recording. The signal reproducing circuit includes a waveform equalizer that equalizes the waveform of the signal based on a waveform equalization target, where D is a one-bit delay operator, previously stored in a storage module. The waveform equalization target is any one of a[1+3D+2D2] [1?D], a[2+5D+2D2] [1?D], and a[1+4D+2D2] [1?D] where a is an integer.

Abstract: Outer side sill member includes an upper wall section slanting upward in a horizontal, outer-to-inner direction, and a lower wall section slanting downward in the horizontal, outer-to-inner direction. At least one of upper and lower wall sections of the outer side sill member has a channel-shaped bead extending along the side sill, so that the side sill has a polygonal closed sectional shape extending in the front-rear direction of the vehicle. The bead has a bottom portion having a width greater than a vertical dimension in a direction orthogonal to the surface of the bottom portion. Each of bulkheads, partitioning the interior of the side sill, is fixedly joined to the outer side sill member with its recessed edge portion substantially fittingly engaging with the bottom portion of the depressed wall portion of the outer side sill member.

Abstract: A semiconductor device includes a semiconductor layer stack 13 formed on a substrate 11 and having a channel region, a first electrode 16A and a second electrode 16B formed spaced apart from each other on the semiconductor layer stack 13, a first gate electrode 18A formed between the first electrode 16A and the second electrode 16B, and a second gate electrode 18B formed between the first gate electrode 18A and the second electrode 16B. A first control layer 19A having a p-type conductivity is formed between the semiconductor layer stack 13 and the first gate electrode 18A.

Abstract: A semiconductor device includes: a semiconductor layer; at least one electrode formed on a semiconductor layer to be in contact with the semiconductor layer; and a passivation film covering the semiconductor layer and at least part of the top surface of the electrode to protect the semiconductor layer and formed of a plurality of sub-films. The passivation film includes a first sub-film made of aluminum nitride.

Abstract: A semiconductor device includes: a semiconductor layer; at least one electrode formed on a semiconductor layer to be in contact with the semiconductor layer; and a passivation film covering the semiconductor layer and at least part of the top surface of the electrode to protect the semiconductor layer and formed of a plurality of sub-films. The passivation film includes a first sub-film made of aluminum nitride.

Abstract: A semiconductor device includes: a semiconductor layer made of a group-III nitride semiconductor and having a first surface and a second surface opposed to the first surface; a Schottky electrode formed on the first surface of the semiconductor layer; and an ohmic electrode electrically connected to the second surface of the semiconductor layer. The semiconductor layer has, in at least the upper portion thereof, highly-resistive regions selectively formed to have a high resistance.

Abstract: A wireless apparatus which can realize a DFS function that avoidance of interference with radar is considered in an Ad-Hoc mode under a multihop circumstance is provided. A Beacon frame is transmitted at a shorter interval than a previously set interval when radar is detected by wireless apparatuses N1 to N6 which have a DFS function which perform avoidance of interference with radar.

Abstract: In a transistor, an AlN buffer layer 102, an undoped GaN layer 103, an undoped AlGaN layer 104, a p-type control layer 105, and a p-type contact layer 106 are formed in this order on a sapphire substrate 101. The transistor further includes a gate electrode 110 in ohmic contact with the p-type contact layer 106, and a source electrode 108 and a drain electrode 109 provided on the undoped AlGaN layer 104. By applying a positive voltage to the p-type control layer 105, holes are injected into a channel to increase a current flowing in the channel.

Abstract: It is an object of the present invention to provide a semiconductor device, which can simultaneously achieve a normally-off mode of HFET and an improvement in Imax, and further achieve an improvement in gm and a reduction in gate leakage current. In order to keep a thin barrier layer 13 on an operation layer 12 of a substrate 11 directly under a gate electrode for mostly contributing to achieve the normally-off mode and also implement the high Imax, it is configured in such a way that a thickness of the barrier layer 13 can be increased by the semiconductor layer 17 between gate and source regions and between gate and drain regions. It is therefore possible to achieve the normally-off mode and an improvement in Imax as compared with an FET in which a thickness of the barrier layer is designed so as to be uniform.

Abstract: According to an aspect of an embodiment, a storage apparatus has a storage for storing a plurality of compensation values in association with a plurality of bit sequence patterns, a head for writing data into a medium and a controller for controlling the apparatus and driving the head, the controller determining whether to use one of the compensation values to drive the head to write an instantaneous data bit in dependence upon the immediate preceding data bits in reference to the bit sequence patterns.

Abstract: A scrambler that facilitates encryption of data to be recorded and a magnetic storage device using this are provided. The scrambler has a shift register of a plurality of stages and an exclusive OR circuit that finds the exclusive OR of the logic of the stages of the shift register that correspond to a single generating polynomial. The output of the exclusive OR circuit is arranged to be fed back to the initial stage of the shift register. At least this single generating polynomial is an arbitrary generating polynomial. The drive number, in binary form, that identifies the storage device, is set as the initial value of the shift register of a plurality of stages.

Abstract: A semiconductor device includes: a semiconductor layer; at least one electrode formed on a semiconductor layer to be in contact with the semiconductor layer; and a passivation film covering the semiconductor layer and at least part of the top surface of the electrode to protect the semiconductor layer and formed of a plurality of sub-films. The passivation film includes a first sub-film made of aluminum nitride.

Abstract: A semiconductor device includes a first group III-V nitride semiconductor layer, a second group III-V nitride semiconductor layer having a larger band gap than the first group Ill-V nitride semiconductor layer and at least one ohmic electrode successively formed on a substrate. The ohmic electrode is formed so as to have a base portion penetrating the second group III-V nitride semiconductor layer and reaching a portion of the first group III-V nitride semiconductor layer disposed beneath a two-dimensional electron gas layer. An impurity doped layer is formed in portions of the first group III-V nitride semiconductor layer and the second group III-V nitride semiconductor layer in contact with the ohmic electrode.

Abstract: In the structure of a semiconductor device of the present invention, a first source electrode is connected to a conductive substrate through a via hole, and a second source electrode is formed. Thus, even if a high reverse voltage is applied between a gate electrode and a drain electrode, electric field concentration likely to occur at an edge of the gate electrode closer to the drain electrode can be effectively dispersed or relaxed. Moreover, the conductive substrate is used as a substrate for forming element formation layers, so that a via hole penetrating the substrate to reach the backside thereof does not have to be formed in the conductive substrate. Thus, with the strength necessary for the conductive substrate maintained, the first source electrode can be electrically connected to a backside electrode.

Abstract: A semiconductor device includes: a semiconductor layer made of a group-III nitride semiconductor and having a first surface and a second surface opposed to the first surface; a Schottky electrode formed on the first surface of the semiconductor layer; and an ohmic electrode electrically connected to the second surface of the semiconductor layer. The semiconductor layer has, in at least the upper portion thereof, highly-resistive regions selectively formed to have a high resistance.