Abstract: A semiconductor integrated circuit includes: a well 35 of a first conductivity type formed on a substrate 37; a first external terminal 10, a second external terminal 11, and a third external terminal 12 provided above the substrate 37; a first protection circuit 20 provided on an electrical path between the first external terminal 10 and the second external terminal 11; a second protection circuit 21 provided on an electrical path between the second external terminal 11 and the third external terminal 12; and a third protection circuit 22 provided on an electrical path between the third external terminal 12 and the first external terminal 10. A guard ring 40 is formed continuously in the well to surround at least two circuits among the first, second, and third protection circuits 20, 21, and 22, formed on the well 35.

Abstract: A semiconductor integrated circuit includes: a well 35 of a first conductivity type formed on a substrate 37; a first external terminal 10, a second external terminal 11, and a third external terminal 12 provided above the substrate 37; a first protection circuit 20 provided on an electrical path between the first external terminal 10 and the second external terminal 11; a second protection circuit 21 provided on an electrical path between the second external terminal 11 and the third external terminal 12; and a third protection circuit 22 provided on an electrical path between the third external terminal 12 and the first external terminal 10. A guard ring 40 is formed continuously in the well to surround at least two circuits among the first, second, and third protection circuits 20, 21, and 22, formed on the well 35.

Abstract: A semiconductor device includes: a gate electrode formed above a semiconductor region; a drain region and a source region formed in portions of the semiconductor region located below sides of the gate electrode in a gate length direction, respectively; a plurality of drain contacts formed on the drain region to be spaced apart in a gate width direction of the gate electrode; and a plurality of source contacts formed on the source region to be spaced apart in the gate width direction of the gate electrode. The intervals between the drain contacts are greater than the intervals between the source contacts.

Abstract: An electro static discharge protection element being formed by a diode including a well region of a first conductivity type on a surface of a semiconductor substrate, and a first diffusion layer of a second conductivity type in the well region. The first diffusion layer is surrounded by a second diffusion layer of the first conductivity type in the well region. The first diffusion layer has a surface on which a first contact region connected to an input/output terminal is formed. The first diffusion layer has a surface on which a second contact region connected to a reference voltage terminal is formed.

Abstract: A semiconductor device includes: a gate electrode formed above a semiconductor region; a drain region and a source region formed in portions of the semiconductor region located below sides of the gate electrode in a gate length direction, respectively; a plurality of drain contacts formed on the drain region to be spaced apart in a gate width direction of the gate electrode; and a plurality of source contacts formed on the source region to be spaced apart in the gate width direction of the gate electrode. The intervals between the drain contacts are greater than the intervals between the source contacts.

Abstract: A semiconductor device includes: a gate electrode formed above a semiconductor region; a drain region and a source region formed in portions of the semiconductor region located below sides of the gate electrode in a gate length direction, respectively; a plurality of drain contacts formed on the drain region to be spaced apart in a gate width direction of the gate electrode; and a plurality of source contacts formed on the source region to be spaced apart in the gate width direction of the gate electrode. The intervals between the drain contacts are greater than the intervals between the source contacts.

Abstract: An electro static discharge protection element being formed by a diode including a well region of a first conductivity type on a surface of a semiconductor substrate, and a first diffusion layer of a second conductivity type in the well region. The first diffusion layer is surrounded by a second diffusion layer of the first conductivity type in the well region. The first diffusion layer has a surface on which a first contact region connected to an input/output terminal is formed. The first diffusion layer has a surface on which a second contact region connected to a reference voltage terminal is formed.

Abstract: A semiconductor integrated circuit includes an external pad, a ground line, a first protection circuit between the external pad and the ground line, and a second protection circuit between the external pad and the ground line. The second protection circuit is formed by a first protection element, a second protection element, and a resistor. With this structure, the resistance value of the resistor is set to an arbitrary value, so that an unnecessary current which would be generated at the time of power-off of the LSI can be decreased to a value which does not deteriorate the reliability of the LSI.

Abstract: A semiconductor device includes a protected circuit and an electrostatic-discharge protection circuit. The electrostatic-discharge protection circuit includes a first well of a first conductivity type and a second well of a second conductivity type formed in contact with each other in a semiconductor substrate, a first impurity diffusion layer of the first conductivity type and a third impurity diffusion layer of the second conductivity type formed apart from each other in the first well, and a second impurity diffusion layer of the second conductivity type and a fourth impurity diffusion layer of the first conductivity type formed apart from each other in the second well. The second and the third impurity diffusion layers are formed adjacent to each other interposing an element isolation region provided across a border between the first and the second wells.

Abstract: The semiconductor integrated circuit device includes: a circuit to be protected connected between a power supply line and a ground line; a first resistance connected to an external input terminal at one terminal and to an input terminal of the circuit to be protected at the other terminal; a first electrostatic discharge protection circuit including a first voltage drop circuit connected to the power supply line at one terminal and to the input terminal of the circuit to be protected at the other terminal; and a second electrostatic discharge protection circuit including a second voltage drop circuit connected to the input terminal of the circuit to be protected at one terminal and to the ground line at the other terminal.

Abstract: A semiconductor integrated circuit includes: a well 35 of a first conductivity type formed on a substrate 37; a first external terminal 10, a second external terminal 11, and a third external terminal 12 provided above the substrate 37; a first protection circuit 20 provided on an electrical path between the first external terminal 10 and the second external terminal 11; a second protection circuit 21 provided on an electrical path between the second external terminal 11 and the third external terminal 12; and a third protection circuit 22 provided on an electrical path between the third external terminal 12 and the first external terminal 10. A guard ring 40 is formed continuously in the well to surround at least two circuits among the first, second, and third protection circuits 20, 21, and 22, formed on the well 35.

Abstract: A semiconductor integrated circuit includes an external pad, a ground line, a first protection circuit between the external pad and the ground line, and a second protection circuit between the external pad and the ground line. The second protection circuit is formed by a first protection element, a second protection element, and a resistor. With this structure, the resistance value of the resistor is set to an arbitrary value, so that an unnecessary current which would be generated at the time of power-off of the LSI can be decreased to a value which does not deteriorate the reliability of the LSI.

Abstract: A semiconductor device includes: a gate electrode formed above a semiconductor region; a drain region and a source region formed in portions of the semiconductor region located below sides of the gate electrode in a gate length direction, respectively; a plurality of drain contacts formed on the drain region to be spaced apart in a gate width direction of the gate electrode; and a plurality of source contacts formed on the source region to be spaced apart in the gate width direction of the gate electrode. The intervals between the drain contacts are greater than the intervals between the source contacts.

Abstract: An electro static discharge protection element being formed by a diode including a well region of a first conductivity type on a surface of a semiconductor substrate, and a first diffusion layer of a second conductivity type in the well region. The first diffusion layer is surrounded by a second diffusion layer of the first conductivity type in the well region. The first diffusion layer has a surface on which a first contact region connected to an input/output terminal is formed. The first diffusion layer has a surface on which a second contact region connected to a reference voltage terminal is formed.

Abstract: An inventive semiconductor integrated circuit device includes: an external connection terminal; an electrostatic discharge protection circuit; an output circuit; an output prebuffer circuit; an input prebuffer circuit; an internal circuit; an inter-power supply electrostatic discharge protection circuit; and a substrate potential control circuit. The substrate potential control circuit includes a capacitor and a resistor. The inter-power supply electrostatic discharge protection circuit includes an NMIS transistor. When a positive surge is applied to the external connection terminal, the substrate potential of the NMIS transistor is also increased. Thus, the NMIS transistor is turned ON, and the positive electrical charge supplied to the external connection terminal is discharged toward a ground line.

Abstract: An inventive semiconductor integrated circuit device includes: an external connection terminal 1; an electrostatic discharge protection circuit 2; an output circuit 3; an output prebuffer circuit 4; an input prebuffer circuit 5; an internal circuit 41; an inter-power supply electrostatic discharge protection circuit 6; and a gate voltage control circuit 7. The gate voltage control circuit 7 has a capacitor 25 and a resistor 26, and the inter-power supply electrostatic discharge protection circuit 6 has an NMIS transistor 24. When a positive surge is applied to the external connection terminal 1, the gate potential of the NMIS transistor 24 is also increased. Thus, the NMIS transistor 24 is turned on, and the positive electrical charge supplied to the external connection terminal 1 is discharged toward a ground line 23.

Abstract: A semiconductor device includes: a gate electrode on a semiconductor substrate; side wall spacers on side surfaces of the gate electrode; a source portion and a drain portion in the semiconductor substrate, the source portion and the drain portion being provided laterally to the side wall spacers; an on-source silicide film on the source portion; an on-drain silicide film on the drain portion; source contacts over the source portion; and at least a pair of drain contacts which are provided over the drain portion and which are aligned in the gate width direction of the gate electrode. Part of the drain portion between the pair of drain contacts includes a high resistance region at least in an area between the side wall spacer and edges of the drain contacts facing the gate electrode such that the on-drain silicide film is not provided in the high resistance region.

Abstract: The semiconductor integrated circuit device includes: a circuit to be protected connected between a power supply line and a ground line; a first resistance connected to an external input terminal at one terminal and to an input terminal of the circuit to be protected at the other terminal; a first electrostatic discharge protection circuit including a first voltage drop circuit connected to the power supply line at one terminal and to the input terminal of the circuit to be protected at the other terminal; and a second electrostatic discharge protection circuit including a second voltage drop circuit connected to the input terminal of the circuit to be protected at one terminal and to the ground line at the other terminal.

Abstract: A semiconductor integrated circuit of the present invention includes, between a power line 1 and a ground line 2, an NMIS transistor 3 capable of supplying fixed signals with low and high levels to the outside, an NMIS transistor 6 having a source connected to a gate of the NMIS transistor 3, a PMIS transistor 7 having a drain connected to a gate of the NMIS transistor 6, and an ESD protection power clamp circuit 14. If a surge is applied to the power line 1, the ESD protection power clamp circuit 14 is clamped to pass the surge to the ground line. While the surge is passed, the potential of the power line 1 rises to turn on the three transistors 3, 6, and 7. At this time, the NMIS transistor 6 and the PMIS transistor 7 can reduce the gate potential of the NMIS transistor 3 lower than the potential of the power line 1.

Abstract: A method for simulating an electrostatic discharge protective circuit replaces an electrostatic discharge protective element having an insulated-gate field-effect transistor having a source and a drain with an equivalent circuit including the insulated-gate field-effect transistor, a bipolar transistor, a current source, a diode, and a substrate resistance. Then, the method applies a forward bias to the source or the drain to perform a first simulation with respect to the equivalent circuit and applies a reverse bias to the source or the drain to perform a second simulation with respect to the equivalent circuit. The diode is disposed to cause, when the forward bias is applied to the source or the drain, a forward diode current to flow to the source or the drain to which the forward bias has been applied.