Abstract: A semiconductor integrated circuit of the present invention includes, between a power line 1 and a ground line 2, an NMIS transistor 3 capable of supplying fixed signals with low and high levels to the outside, an NMIS transistor 6 having a source connected to a gate of the NMIS transistor 3, a PMIS transistor 7 having a drain connected to a gate of the NMIS transistor 6, and an ESD protection power clamp circuit 14. If a surge is applied to the power line 1, the ESD protection power clamp circuit 14 is clamped to pass the surge to the ground line. While the surge is passed, the potential of the power line 1 rises to turn on the three transistors 3, 6, and 7. At this time, the NMIS transistor 6 and the PMIS transistor 7 can reduce the gate potential of the NMIS transistor 3 lower than the potential of the power line 1.

Abstract: An inventive semiconductor integrated circuit device includes: an external connection terminal; an electrostatic discharge protection circuit; an output circuit; an output prebuffer circuit; an input prebuffer circuit; an internal circuit; an inter-power supply electrostatic discharge protection circuit; and a substrate potential control circuit. The substrate potential control circuit includes a capacitor and a resistor. The inter-power supply electrostatic discharge protection circuit includes an NMIS transistor. When a positive surge is applied to the external connection terminal, the substrate potential of the NMIS transistor is also increased. Thus, the NMIS transistor is turned ON, and the positive electrical charge supplied to the external connection terminal is discharged toward a ground line.

Abstract: An inventive semiconductor integrated circuit device includes: an external connection terminal 1; an electrostatic discharge protection circuit 2; an output circuit 3; an output prebuffer circuit 4; an input prebuffer circuit 5; an internal circuit 41; an inter-power supply electrostatic discharge protection circuit 6; and a gate voltage control circuit 7. The gate voltage control circuit 7 has a capacitor 25 and a resistor 26, and the inter-power supply electrostatic discharge protection circuit 6 has an NMIS transistor 24. When a positive surge is applied to the external connection terminal 1, the gate potential of the NMIS transistor 24 is also increased. Thus, the NMIS transistor 24 is turned on, and the positive electrical charge supplied to the external connection terminal 1 is discharged toward a ground line 23.

Abstract: The system comprises a central processing unit which processes received data, a memory unit which stores programs required for the operations of this central processing unit and other data, a data transmission adapter which receives the data, an output control unit which delivers the received data to each output end under the control of said central processing unit, and a mode setting unit which stores output mode data for setting an output mode at each output end when the received data are abnormal. When the received data are abnormal, the output mode data and the output data outputted already to the output control unit are taken in, said output data are modified into those in an output mode designated by the output mode data, and the output data thus modified are delivered to the output control unit.

Abstract: An apparatus for controlling the running track of a trackless moving body comprising a guide wire, a position deviation sensor unit mounted on the trackless moving body for sensing a deviation of the position of the moving body relative to the guide wire, a steering control circuit connected to the position deviation sensor unit, and a steering drive unit connected to the steering control circuit for steering the moving body. The steering control circuit comprises a first-order lag circuit receiving the output signal from the position deviation sensor unit, a subtractor receiving the output signal from the position deviation sensor unit and the output signal from the first-order lag circuit, and a comparator receiving the output signal from the subtractor.