Patents by Inventor Hirofumi Inoue

Hirofumi Inoue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8391045
    Abstract: An information recording/reproducing device includes a first electrode layer, a second electrode layer, a recording layer as a variable resistance between the first and second electrode layer, and a circuit which supplies a voltage to the recording layer to change a resistance of the recording layer. Each of the first and second electrode layers is comprised of IV or III-V semiconductor doped with p-type carrier or n-type carrier.
    Type: Grant
    Filed: September 21, 2009
    Date of Patent: March 5, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kohichi Kubo, Hirofumi Inoue, Mitsuru Sato, Chikayoshi Kamata, Shinya Aoki, Noriko Bota
  • Patent number: 8391082
    Abstract: A nonvolatile semiconductor memory device comprises a cell array including plural MATs (unit cell arrays) arranged in matrix, each MAT containing a plurality of first lines, a plurality of second lines intersecting the plurality of first lines, and a plurality of memory cells connected at intersections of the first and second lines between both lines, each memory cell containing an electrically erasable programmable variable resistive element of which resistance is stored in a non-volatile manner as data; and a plurality of write/erase circuits connected to the MATs and operative to execute data write or erase to the memory cells inside the MATs in accordance with input data. A part of the plurality of write/erase circuits writes data to memory cells inside a corresponding MAT while another part of the plurality of write/erase circuits erases data from memory cells inside a corresponding MAT at the same time.
    Type: Grant
    Filed: May 3, 2011
    Date of Patent: March 5, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki Nagashima, Hirofumi Inoue
  • Patent number: 8391048
    Abstract: A non-volatile semiconductor memory device according to an aspect of embodiments of the present invention includes a memory cell array including: multiple first wirings; multiple second wirings crossing the multiple first wirings; and multiple electrically rewritable memory cells respectively arranged at intersections of the first wirings and the second wirings, and each formed of a variable resistor which stores a resistance value as data in a non-volatile manner. The non-volatile semiconductor memory device according to an aspect of the embodiments of the present invention further includes a controller for selecting a given one of the memory cells, generating an erase pulse which is used for erasing data, and supplying the erase pulse to the selected memory cell. The erase pulse has a pulse width which is increased or decreased exponentially in accordance with an access path length to the selected memory cell.
    Type: Grant
    Filed: July 29, 2010
    Date of Patent: March 5, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Reika Ichihara, Takayuki Tsukamoto, Kenichi Murooka, Hirofumi Inoue, Hiroshi Kanno
  • Patent number: 8370022
    Abstract: A suspension system is provided to execute a control for avoiding a state in which an operation of an electric motor which is a power source of an electromagnetic actuator is kept halted at a certain operational position while the motor is generating a motor force. Where a target rotational position of the motor becomes equal to a specific operational position (e.g., a rotational position at which an electrifying current amount of one phase reaches a peak value), a control for shifting the target rotational position by ?? is executed. Where the rotational position of the motor is kept located at the certain position for a time period longer than a prescribed time, a control for changing the rotational position of the motor is executed.
    Type: Grant
    Filed: January 13, 2012
    Date of Patent: February 5, 2013
    Assignees: Toyota Jidosha Kabushiki Kaisha, Kayaba Industry Co., Ltd.
    Inventors: Hirofumi Inoue, Hideshi Watanabe, Takuhiro Kondo
  • Patent number: 8318602
    Abstract: According to an aspect of the present invention, there is provided a nonvolatile semiconductor storage apparatus including: a substrate; a columnar semiconductor disposed perpendicular to the substrate; a charge storage laminated film disposed around the columnar semiconductor; a first conductor layer that is in contact with the charge storage laminated film and that has a first end portion having a first end face; a second conductor layer that is in contact with the charge storage laminated film, that is separated from the first conductor layer and that has a second end portion having a second end face; a first contact plug disposed on the first end face; and a second contact plug disposed on the second end face.
    Type: Grant
    Filed: April 13, 2011
    Date of Patent: November 27, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masaru Kito, Hirofumi Inoue
  • Patent number: 8320158
    Abstract: Nonvolatile semiconductor memory device of an embodiment includes: a memory cell array including a plurality of first and second lines intersecting each other and plural memory cells provided at intersections of the first and second lines and having data written and erased upon application of voltages of the same polarity; and a writing circuit configured to select first and second lines and supply a set or reset pulse to the memory cell through the selected first and second lines. In an erase operation, the writing circuit repeatedly supplies the reset pulse to a selected memory cell until data is erased, by increasing or decreasing voltage level and voltage application time of the reset pulse within a reset region. The reset region, or an aggregate of combinations of voltage level and voltage application time of the reset pulse, is a region where voltage level and voltage application time are negatively correlated.
    Type: Grant
    Filed: September 15, 2010
    Date of Patent: November 27, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Kanno, Reika Ichihara, Takayuki Tsukamoto, Kenichi Murooka, Hirofumi Inoue
  • Patent number: 8285448
    Abstract: It is an object of the invention to provide a suspension system configured to execute a control for avoiding a state in which an operation of an electric motor which is a power source of an electromagnetic actuator is kept halted at a certain operational position while the motor is generating a motor force. Where a target rotational position of the motor becomes equal to a specific operational position (e.g., a rotational position at which an electrifying current amount of one phase reaches a peak value), a control for shifting the target rotational position by ?? is executed. Where the rotational position of the motor is kept located at the certain position for a time period longer than a prescribed time, a control for changing the rotational position of the motor is executed. According to the present suspension system, it is possible to suppress imbalance in heat generation in the motor and to thereby reduce a load to be applied to the motor. Accordingly, a suspension system with high utility is realized.
    Type: Grant
    Filed: August 28, 2007
    Date of Patent: October 9, 2012
    Assignees: Toyota Jidosha Kabushiki Kaisha, Kayaba Industry Co., Ltd.
    Inventors: Hirofumi Inoue, Hideshi Watanabe, Takuhiro Kondo
  • Patent number: 8259489
    Abstract: A nonvolatile semiconductor memory device comprises a memory cell array of electrically erasable programmable nonvolatile memory cells arranged in matrix, each memory cell using a variable resistor. A pulse generator is operative to generate plural types of write pulses for varying the resistance of the variable resistor in three or more stages based on ternary or higher write data. A selection circuit is operative to select a write target memory cell from the memory cell array based on a write address and supply the write pulse generated from the pulse generator to the selected memory cell.
    Type: Grant
    Filed: September 9, 2008
    Date of Patent: September 4, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki Nagashima, Hirofumi Inoue, Haruki Toda
  • Patent number: 8254160
    Abstract: According to one embodiment, a semiconductor memory device includes: word lines; bit lines; an insulating film; an interlayer insulating film; and a resistance varying material. The word lines, the bit lines and the insulating film configure a field-effect transistor at each of the intersections of the word lines and the bit lines. The field-effect transistor has one of the word lines as a control electrode and one of the bit lines as a channel region. The field-effect transistor and the resistance varying material configure a memory cell having the field-effect transistor and the resistance varying material connected in parallel. Each of the bit lines includes a first surface opposing the word lines, and a second surface on an opposite side to the first surface. The resistance varying material is disposed in contact with the second surface and has a portion thereof in contact with the interlayer insulating film.
    Type: Grant
    Filed: September 21, 2010
    Date of Patent: August 28, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenichi Murooka, Hirofumi Inoue
  • Publication number: 20120205612
    Abstract: A nonvolatile semiconductor memory device comprises a semiconductor substrate; a cell array block formed on the semiconductor substrate and including plural stacked cell array layers each with a plurality of first lines, a plurality of second lines crossing the plurality of first lines, and memory cells connected at intersections of the first and second lines between both lines; and a plurality of via-holes extending in the stacked direction of the cell array layers to individually connect the first or second line in the each cell array layer to the semiconductor substrate. The via-holes are formed continuously through the plural cell array layers, and multiple via-holes having equal lower end positions and upper end positions are connected to the first or second lines in different cell array layers.
    Type: Application
    Filed: April 24, 2012
    Publication date: August 16, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hideyuki TABATA, Eiji ITO, Hirofumi INOUE
  • Patent number: 8191874
    Abstract: A vehicle suspension system including: (a) a suspension spring interconnecting a vehicle body and a wheel; (b) an actuator having an electric motor, such that the actuator is capable of generating, based on a force of the electric motor, an actuator force forcing the body and the wheel toward and away from each other, and causing the generated actuator force to act as a damping force against displacement of the body and the wheel; and (c) a control device for controlling the actuator force generated by the actuator, by controlling operation of the electric motor. The control device is capable of establishing a constant-force generating state in which the actuator force is constantly generated as a constant actuator force by the actuator with supply of an electric power thereto from a battery as an electric power source of the electric motor such that the generated constant actuator force acts in a rebound direction or a bound direction.
    Type: Grant
    Filed: March 6, 2007
    Date of Patent: June 5, 2012
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Hirofumi Inoue, Hiroaki Date, Kazuo Ogawa
  • Patent number: 8183671
    Abstract: A semiconductor device includes a device isolation insulating film which is buried in a semiconductor substrate, a gate insulation film which is provided on the semiconductor substrate, a gate electrode which is provided on the gate insulation film, a source region and a drain region which are provided in the semiconductor substrate and spaced apart from each other in a manner to sandwich the gate electrode, both end portions of each of the source region and the drain region being offset from the device isolation insulating film in a channel width direction by a predetermined distance, and first and second gate electrode extension portions which are provided in a manner to cover both end portions of each of the source region and the drain region in a channel length direction.
    Type: Grant
    Filed: December 13, 2011
    Date of Patent: May 22, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shinichi Watanabe, Hirofumi Inoue
  • Patent number: 8183602
    Abstract: A nonvolatile semiconductor memory device comprises a semiconductor substrate; a cell array block formed on the semiconductor substrate and including plural stacked cell array layers each with a plurality of first lines, a plurality of second lines crossing the plurality of first lines, and memory cells connected at intersections of the first and second lines between both lines; and a plurality of via-holes extending in the stacked direction of the cell array layers to individually connect the first or second line in the each cell array layer to the semiconductor substrate. The via-holes are formed continuously through the plural cell array layers, and multiple via-holes having equal lower end positions and upper end positions are connected to the first or second lines indifferent cell array layers.
    Type: Grant
    Filed: November 21, 2008
    Date of Patent: May 22, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideyuki Tabata, Eiji Ito, Hirofumi Inoue
  • Publication number: 20120116634
    Abstract: A suspension system is provided to execute a control for avoiding a state in which an operation of an electric motor which is a power source of an electromagnetic actuator is kept halted at a certain operational position while the motor is generating a motor force. Where a target rotational position of the motor becomes equal to a specific operational position (e.g., a rotational position at which an electrifying current amount of one phase reaches a peak value), a control for shifting the target rotational position by ?? is executed. Where the rotational position of the motor is kept located at the certain position for a time period longer than a prescribed time, a control for changing the rotational position of the motor is executed.
    Type: Application
    Filed: January 13, 2012
    Publication date: May 10, 2012
    Applicants: KAYABA INDUSTRY CO., LTD., TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Hirofumi Inoue, Hideshi Watanabe, Takuhiro Kondo
  • Publication number: 20120080741
    Abstract: A semiconductor device includes a device isolation insulating film which is buried in a semiconductor substrate, a gate insulation film which is provided on the semiconductor substrate, a gate electrode which is provided on the gate insulation film, a source region and a drain region which are provided in the semiconductor substrate and spaced apart from each other in a manner to sandwich the gate electrode, both end portions of each of the source region and the drain region being offset from the device isolation insulating film in a channel width direction by a predetermined distance, and first and second gate electrode extension portions which are provided in a manner to cover both end portions of each of the source region and the drain region in a channel length direction.
    Type: Application
    Filed: December 13, 2011
    Publication date: April 5, 2012
    Inventors: Shinichi Watanabe, Hirofumi Inoue
  • Patent number: 8127900
    Abstract: An electromagnetic shock absorber including: (a) a wheel-side member; (b) a body-side member movable relative to the wheel-side member; and (c) a damping force generator with an electromagnetic motor including stationary and movable elements movable relative to each other. The damping force generator can generate, based on a force generated by the motor, a damping force acting against a relative movement of the wheel-side member and the body-side member. The motor has an axis extending in a both-members-relative-movement direction as a direction of the above-described relative movement. The stationary element is supported by the wheel-side member via an elastic body, to be movable relative to the wheel-side member in the both-members-relative-movement direction. The electromagnetic motor allows relative movement of the stationary element and the movable element upon movement of the stationary element relative to the wheel-side member.
    Type: Grant
    Filed: September 21, 2006
    Date of Patent: March 6, 2012
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventor: Hirofumi Inoue
  • Patent number: 8120942
    Abstract: A memory array includes a memory cell, the memory cell being disposed between a first line and a second line and being configured by a variable resistor and a rectifier connected in series. The variable resistor is a mixture of silicon oxide (SiO2) and a transition metal oxide, a proportion of the transition metal oxide being set to 55˜80%.
    Type: Grant
    Filed: September 15, 2009
    Date of Patent: February 21, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeshi Yamaguchi, Mariko Hayashi, Hirofumi Inoue, Takeshi Araki, Koichi Kubo
  • Patent number: 8110867
    Abstract: A semiconductor device includes a device isolation insulating film which is buried in a semiconductor substrate, a gate insulation film which is provided on the semiconductor substrate, a gate electrode which is provided on the gate insulation film, a source region and a drain region which are provided in the semiconductor substrate and spaced apart from each other in a manner to sandwich the gate electrode, both end portions of each of the source region and the drain region being offset from the device isolation insulating film in a channel width direction by a predetermined distance, and first and second gate electrode extension portions which are provided in a manner to cover both end portions of each of the source region and the drain region in a channel length direction.
    Type: Grant
    Filed: September 29, 2008
    Date of Patent: February 7, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shinichi Watanabe, Hirofumi Inoue
  • Patent number: 8109371
    Abstract: A damper is comprised of an actuator (A) connected to a sprung member (B) side of a vehicle, the actuator (A) including a motion converting mechanism (T) for transforming a linear motion into a rotational motion and a motor (M) to which the rotational motion resulting from the transformation by the motion converting mechanism (T) is transmitted; a hydraulic damper (E) including a cylinder (C), a piston (P) inserted slidably into the cylinder (C) and defining two pressure chambers within the cylinder (C), and a rod (R) connected at one end thereof to the piston (P), wherein a linear motion of the actuator (A) being transmitted to one of the rod (R) and the cylinder (C) while the other of the rod (R) and the cylinder (C) being connected to an unsprung member (W) side of the vehicle; and biasing means (1, 2, X, Y, Z) for biasing the hydraulic damper (E) in both compressing and extending directions.
    Type: Grant
    Filed: November 7, 2006
    Date of Patent: February 7, 2012
    Assignees: Kayaba Industry Co., Ltd., Toyota Jidosha Kabushiki Kaisha
    Inventors: Takuhiro Kondo, Hirofumi Inoue
  • Patent number: 8103408
    Abstract: In a system including four electromagnetic absorbers for respective four vehicle wheels, motor coils of two respective electromagnetic absorbers disposed corresponding to two diagonally located wheels are connected forming a closed loop including the coils. A generated damping force magnitude can be made different between an instance directions of respective movements of the diagonally located two wheels with respect to the vehicle body are the same, and an instance the directions are opposite each other. Each electromagnetic absorber includes a resistor cooperating with the corresponding coil forming a closed loop, and selectively establishes: a connected state in which one of the four coils and any of the other three coils are connected to form a closed loop; and a non-connected state in which the one of the four coils is not connected to any other coil. An appropriate vibration suppressing action is exhibited with respect to a coupled motion.
    Type: Grant
    Filed: October 25, 2006
    Date of Patent: January 24, 2012
    Assignees: Toyota Jidosha Kabushiki Kaisha, Kayaba Industry Co., Ltd., The University of Tokyo
    Inventors: Hirofumi Inoue, Takuhiro Kondo, Yoshihiro Suda