Abstract: A damper is comprised of an actuator (A) connected to a sprung member (B) side of a vehicle, the actuator (A) including a motion converting mechanism (T) for transforming a linear motion into a rotational motion and a motor (M) to which the rotational motion resulting from the transformation by the motion converting mechanism (T) is transmitted; a hydraulic damper (E) including a cylinder (C), a piston (P) inserted slidably into the cylinder (C) and defining two pressure chambers within the cylinder (C), and a rod (R) connected at one end thereof to the piston (P), wherein a linear motion of the actuator (A) being transmitted to one of the rod (R) and the cylinder (C) while the other of the rod (R) and the cylinder (C) being connected to an unsprung member (W) side of the vehicle; and biasing means (1, 2, X, Y, Z) for biasing the hydraulic damper (E) in both compressing and extending directions.

Abstract: In a system including four electromagnetic absorbers for respective four vehicle wheels, motor coils of two respective electromagnetic absorbers disposed corresponding to two diagonally located wheels are connected forming a closed loop including the coils. A generated damping force magnitude can be made different between an instance directions of respective movements of the diagonally located two wheels with respect to the vehicle body are the same, and an instance the directions are opposite each other. Each electromagnetic absorber includes a resistor cooperating with the corresponding coil forming a closed loop, and selectively establishes: a connected state in which one of the four coils and any of the other three coils are connected to form a closed loop; and a non-connected state in which the one of the four coils is not connected to any other coil. An appropriate vibration suppressing action is exhibited with respect to a coupled motion.

Abstract: A semiconductor memory device in an embodiment comprises memory cells, each of the memory cells disposed between a first line and a second line and having a variable resistance element and a switching element connected in series. The variable resistance element includes a variable resistance layer configured to change in resistance value thereof between a low-resistance state and a high-resistance state. The variable resistance layer is configured by a transition metal oxide. A ratio of transition metal and oxygen configuring the transition metal oxide varies between 1:1 and 1:2 along a first direction directed from the first line to the second line.

Abstract: A resistance change memory device includes: a memory cell array with memory cells arranged therein, the memory cell having a variable resistance element for storing a rewritable resistance value; a reference cell formed of the same memory cells as those set in a high resistance state in the memory cell array, the reference cell being trimmed with selection of the number of parallel-connected memory cells to have a reference current value used for detecting data in the memory cell array; and a sense amplifier configured to compare a cell current value of a memory cell selected in the memory cell array with the reference current value of the reference cell.

Abstract: A discharge gap filling composition for an electrostatic discharge protector. The composition contains oxide film coated metal particles (A), a layered substance (B) and a binder component (C). Also disclosed is an electrostatic discharge protector including a discharge gap and a discharge gap filling material containing the discharge gap filling composition that is filled in the discharge gap.

Abstract: A semiconductor memory device includes a memory block having a three-dimensional memory cell array structure in which memory cell arrays are stacked, the memory cell array including: a plurality of first interconnections which are parallel to one another; a plurality of second interconnections which are formed so as to intersect with the plurality of first interconnections, the second interconnections being parallel to one another; and a memory cell which is disposed in each intersection portion of the first interconnection and the second interconnection, one end of the memory cell being connected to the first interconnection, the other end of the memory cell being connected to the second interconnection. The first interconnection disposed between the adjacent memory cell arrays is shared by memory cells above and below the first interconnection, and the vertically-overlapping first interconnections are connected to each other.

Abstract: A vehicle damper including an electromagnetic damper configured to generate a damping force with respect to a motion of a sprung portion and an unsprung portion toward each other and a motion thereof away from each other and includes: an electromagnetic motor; a motion converting mechanism; and an external circuit which is disposed outside the electromagnetic motor and including a first connection passage and a second connection passage and which includes a battery-device connection circuit for connecting the motor and a battery device and a battery-device-connection-circuit-current adjuster configured to adjust an electric current that flows in the battery-device connection circuit, wherein the damper system further includes an external-circuit controller configured to control an electric current that flows in the electromagnetic motor by controlling the external circuit and configured to control a flow of an electric current between the battery device and the electromagnetic motor by controlling the battery

Abstract: A cell array includes a memory cell region in which memory cells are formed and a peripheral region that is provided around the memory cell region. In the memory cell region, first lines are extended in parallel with a first direction, and the first lines are repeatedly formed at first intervals in a second direction orthogonal to the first direction. In the peripheral region, each of the first lines located at (4n?3)-th (n is a positive integer) and (4n?2)-th positions in the second direction from a predetermined position has a contact connecting portion on one end side in the first direction of the first line. In the peripheral region, each of the first lines located at (4n?1)-th and 4n-th positions in the second direction from the predetermined position has the contact connecting portion on the other end side in the first direction of the first line. The contact connecting portion is formed so as to contact a contact plug extended in a laminating direction.

Abstract: A nonvolatile semiconductor memory device comprises a cell array including a plurality of first lines, a plurality of second lines intersecting the plurality of first lines, and a plurality of memory cells arranged in matrix and connected at intersections of the first and second lines between both lines, each memory cell containing a serial circuit of an electrically erasable programmable variable resistive element of which resistance is nonvolatilely stored as data and a non-ohmic element; and a plurality of access circuits operative to simultaneously access the memory cells physically separated from each other in the cell array.

Abstract: A semiconductor memory device includes a memory block having a three-dimensional memory cell array structure in which memory cell arrays are stacked, the memory cell array including: a plurality of first interconnections which are parallel to one another; a plurality of second interconnections which are formed so as to intersect with the plurality of first interconnections, the second interconnections being parallel to one another; and a memory cell which is disposed in each intersection portion of the first interconnection and the second interconnection, one end of the memory cell being connected to the first interconnection, the other end of the memory cell being connected to the second interconnection. The first interconnection disposed between the adjacent memory cell arrays is shared by memory cells above and below the first interconnection, and the vertically-overlapping first interconnections are connected to each other.

Abstract: A resistance change memory device includes: a memory cell array with memory cells arranged therein, the memory cell having a variable resistance element for storing a rewritable resistance value; a reference cell formed of the same memory cells as those set in a high resistance state in the memory cell array, the reference cell being trimmed with selection of the number of parallel-connected memory cells to have a reference current value used for detecting data in the memory cell array; and a sense amplifier configured to compare a cell current value of a memory cell selected in the memory cell array with the reference current value of the reference cell.

Abstract: A semiconductor memory device includes a memory block having a three-dimensional memory cell array structure in which memory cell arrays are stacked, the memory cell array including: a plurality of first interconnections which are parallel to one another; a plurality of second interconnections which are formed so as to intersect with the plurality of first interconnections, the second interconnections being parallel to one another; and a memory cell which is disposed in each intersection portion of the first interconnection and the second interconnection, one end of the memory cell being connected to the first interconnection, the other end of the memory cell being connected to the second interconnection. The first interconnection disposed between the adjacent memory cell arrays is shared by memory cells above and below the first interconnection, and the vertically-overlapping first interconnections are connected to each other.

Abstract: A change of performance of an electromagnetic suspension unit is detected. When an integral ?|Vs??Vs*| of an absolute value of a difference between an actual value Vs* and an estimated value Vs? of an expansion/contraction velocity of a shock absorber is larger than a performance change threshold value Sth, it is detected that the performance of the electromagnetic suspension unit is changed. Further, when an integral ?|Vs*| of an absolute value of the actual value Vs* is larger than an integral ?|Vs?| of an absolute value of the estimated value Vs? by a predetermined value, performance of the shock absorber is changed such that a damping force of the shock absorber is reduced. Thus, the performance change of the electromagnetic suspension unit is detected based on the expansion/contraction velocity of the shock absorber.

Abstract: A nonvolatile semiconductor memory device comprises a cell array including plural MATs (unit cell arrays) arranged in matrix, each MAT containing a plurality of first lines, a plurality of second lines intersecting the plurality of first lines, and a plurality of memory cells connected at intersections of the first and second lines between both lines, each memory cell containing an electrically erasable programmable variable resistive element of which resistance is nonvolatilely stored as data; and a plurality of write/erase circuits connected to the MATs and operative to execute data write or erase to the memory cells inside the MATs in accordance with input data. A part of the plurality of write/erase circuits writes data to memory cells inside a corresponding MAT while another part of the plurality of write/erase circuits erases data from memory cells inside a corresponding MAT at the same time.

Abstract: The present invention provides an electrostatic discharge protector capable of protecting electronic circuit boards having various designs from electrostatic discharge freely, simply and easily. The electrostatic discharge protector of the present invention comprises at least three conductive members containing one pair of electrodes and the conductive members other than the electrodes, the conductive members are each disposed in such a way that the gap between one conductive member and the other conductive member has a width of 0.1 to 10 ?m, an insulating member is disposed and embedded in at least one of gaps having a width of 0.1 to 10 ?m which are adjacent to each conductive member and one electrode is connected to the other electrode paired with the one electrode through the insulating member and the conductive members other than electrodes.

Abstract: According to an aspect of the present invention, there is provided a nonvolatile semiconductor storage apparatus including: a substrate; a columnar semiconductor disposed perpendicular to the substrate; a charge storage laminated film disposed around the columnar semiconductor; a first conductor layer that is in contact with the charge storage laminated film and that has a first end portion having a first end face; a second conductor layer that is in contact with the charge storage laminated film, that is separated from the first conductor layer and that has a second end portion having a second end face; a first contact plug disposed on the first end face; and a second contact plug disposed on the second end face.

Abstract: A nonvolatile semiconductor memory device comprises a cell array including plural MATs (unit cell arrays) arranged in matrix, each MAT containing a plurality of first lines, a plurality of second lines intersecting the plurality of first lines, and a plurality of memory cells connected at intersections of the first and second lines between both lines, each memory cell containing an electrically erasable programmable variable resistive element of which resistance is nonvolatilely stored as data; and a plurality of write/erase circuits connected to the MATs and operative to execute data write or erase to the memory cells inside the MATs in accordance with input data. A part of the plurality of write/erase circuits writes data to memory cells inside a corresponding MAT while another part of the plurality of write/erase circuits erases data from memory cells inside a corresponding MAT at the same time.

Abstract: According to an aspect of the present invention, there is provided a nonvolatile semiconductor storage apparatus including: a substrate; a columnar semiconductor disposed perpendicular to the substrate; a charge storage laminated film disposed around the columnar semiconductor; a first conductor layer that is in contact with the charge storage laminated film and that has a first end portion having a first end face; a second conductor layer that is in contact with the charge storage laminated film, that is separated from the first conductor layer and that has a second end portion having a second end face; a first contact plug disposed on the first end face; and a second contact plug disposed on the second end face.

Abstract: According to one embodiment, a semiconductor memory device includes: word lines; bit lines; an insulating film; an interlayer insulating film; and a resistance varying material. The word lines, the bit lines and the insulating film configure a field-effect transistor at each of the intersections of the word lines and the bit lines. The field-effect transistor has one of the word lines as a control electrode and one of the bit lines as a channel region. The field-effect transistor and the resistance varying material configure a memory cell having the field-effect transistor and the resistance varying material connected in parallel. Each of the bit lines includes a first surface opposing the word lines, and a second surface on an opposite side to the first surface. The resistance varying material is disposed in contact with the second surface and has a portion thereof in contact with the interlayer insulating film.

Abstract: Nonvolatile semiconductor memory device of an embodiment includes: a memory cell array including a plurality of first and second lines intersecting each other and plural memory cells provided at intersections of the first and second lines and having data written and erased upon application of voltages of the same polarity; and a writing circuit configured to select first and second lines and supply a set or reset pulse to the memory cell through the selected first and second lines. In an erase operation, the writing circuit repeatedly supplies the reset pulse to a selected memory cell until data is erased, by increasing or decreasing voltage level and voltage application time of the reset pulse within a reset region. The reset region, or an aggregate of combinations of voltage level and voltage application time of the reset pulse, is a region where voltage level and voltage application time are negatively correlated.