Abstract: A process program such as an erasing/programming program is stored in a boot mat in a nonvolatile memory operational in a boot mode specified after reset start, and a transfer control program for the process program is also stored therein in advance. With an action of setting control information to a predetermined register as trigger, the state of an on-chip CPU is changed from placed in execution of an optional user program to enabled for execution of a transfer control program in the boot mat, and the CPU is returned to the re-execution state of the optional program, after the process program is transferred to an on-chip RAM.

Abstract: A microcomputer is capable of having a CPU calculate a suitable bit rate with respect to a host computer and of setting accordingly an appropriate erasure time forestalling excess erasure of an internally furnished flash memory regardless of the operating frequency of the microcomputer. The microcomputer includes a central processing unit, a non-volatile semiconductor memory, and a terminal which is supplied with a mode set signal. The non-volatile semiconductor memory includes a first block storing a control program and a second block storing data. When the terminal is supplied with a mode set signal for indicating a predetermined mode, if data has previously been written into the second block, such data is erased by the central processing unit. On the other hand, if no data is found in the second block, it is determined that an erase operation is unnecessary and therefore is not performed.

Abstract: A microcomputer capable of having a CPU calculate a suitable bit rate with respect to a host computer and of setting accordingly an appropriate erasure time forestalling excess erasure of an internally furnished flash memory regardless of the operating frequency of the microcomputer.

Abstract: A semiconductor device having and electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of individual units of plural memory cells. The semiconductor device which functions as a microcomputer chip also has a processing unit and includes an input terminal for receiving an operation mode signal for switching the microcomputer between a first operation mode in which the flash memory is rewritten under control of a processing unit and a second operation mode in which the flash memory is rewritten under control of separate writing circuit externally connectable to the microcomputer.

Abstract: A semiconductor device having and electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of individual units of plural memory cells. The semiconductor device which functions as a microcomputer chip also has a processing unit and includes an input terminal for receiving an operation mode signal for switching the microcomputer between a first operation mode in which the flash memory is rewritten under control of a processing unit and a second operation mode in which the flash memory is rewritten under control of separate writing circuit externally connectable to the microcomputer.

Abstract: A semiconductor device having and electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of individual units of plural memory cells. The semiconductor device which functions as a microcomputer chip also has a processing unit and includes an input terminal for receiving an operation mode signal for switching the microcomputer between a first operation mode in which the flash memory is rewritten under control of a processing unit and a second operation mode in which the flash memory is rewritten under control of separate writing circuit externally connectable to the microcomputer.

Abstract: A semiconductor device having and electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of individual units of plural memory cells. The semiconductor device which functions as a microcomputer chip also has a processing unit and includes an input terminal for receiving an operation mode signal for switching the microcomputer between a first operation mode in which the flash memory is rewritten under control of a processing unit and a second operation mode in which the flash memory is rewritten under control of separate writing circuit externally connectable to the microcomputer.

Abstract: A semiconductor device having and electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of individual units of plural memory cells. The semiconductor device which functions as a microcomputer chip also has a processing unit and includes an input terminal for receiving an operation mode signal for switching the microcomputer between a first operation mode in which the flash memory is rewritten under control of a processing unit and a second operation mode in which the flash memory is rewritten under control of separate writing circuit externally connectable to the microcomputer.

Abstract: A semiconductor device having and electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of individual units of plural memory cells. The semiconductor device which functions as a microcomputer chip also has a processing unit and includes an input terminal for receiving an operation mode signal for switching the microcomputer between a first operation mode in which the flash memory is rewritten under control of a processing unit and a second operation mode in which the flash memory is rewritten under control of separate writing circuit externally connectable to the microcomputer.

Abstract: A microcomputer is capable of having a CPU calculate a suitable bit rate with respect to a host computer, and of setting accordingly an appropriate erasure time forestalling excess erasure of an internally furnished flash memory, regardless of the operating frequency of the microcomputer. The erasure time is set according to a number of clock signal cycles calculated by the CPU, based upon a measured number of cycles taken during a predetermined period of receiving serial data from the host computer.

Abstract: A semiconductor device having and electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of individual units of plural memory cells. The semiconductor device which functions as a microcomputer chip also has a processing unit and includes an input terminal for receiving an operation mode signal for switching the microcomputer between a first operation mode in which the flash memory is rewritten under control of a processing unit and a second operation mode in which the flash memory is rewritten under control of separate writing circuit externally connectable to the microcomputer.

Abstract: A semiconductor device having and electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of individual units of plural memory cells. The semiconductor device which functions as a microcomputer chip also has a processing unit and includes an input terminal for receiving an operation mode signal for switching the microcomputer between a first operation mode in which the flash memory is rewritten under control of a processing unit and a second operation mode in which the flash memory is rewritten under control of separate writing circuit externally connectable to the microcomputer.

Abstract: A semiconductor integrated circuit device having a processing unit and a memory which stores data to be processed by the processing unit and which provides data to the processing unit through the data bus in response to accessing instructions from the processing unit through the address bus. The memory has a plurality of memory blocks each of which has a plurality of electrically programmable nonvolatile memory cells arranged in rows and columns in which each nonvolatile memory cell is coupled to one of a plurality of word lines and one of a plurality of data lines of the memory. The memory blocks formed can be facilitated with different memory capacities, including through controlling the number of rows or columns of memory cells associated therewith.

Abstract: A semiconductor device having and electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of individual units of plural memory cells. The semiconductor device which functions as a microcomputer chip also has a processing unit and includes an input terminal for receiving an operation mode signal for switching the microcomputer between a first operation mode in which the flash memory is rewritten under control of a processing unit and a second operation mode in which the flash memory is rewritten under control of separate writing circuit externally connectable to the microcomputer.

Abstract: A single chip semiconductor integrated circuit device having a central processing unit (CPU) and a flash memory which stores data to be processed by the CPU and which provides data to the CPU through the data bus in response to accessing instructions from the CPU through the address bus. The flash memory is constituted by a plurality of memory blocks each of which has a plurality of electrically programmable nonvolatile memory cells arranged in rows and columns in which each nonvolatile memory cell is coupled to one of a plurality of word lines and one of a plurality of data lines of the flash memory. The memory blocks formed can be facilitated with different memory capacities, including through controlling the number of rows or columns of memory cells associated therewith.

Abstract: A system includes a microcomputer. The microcomputer includes a clock signal circuit, a measuring circuit, a central processing unit, and a flash memory. A user sets a frequency of a clock signal provided by the clock signal circuit. The measuring unit counts a number of cycles of the clock signal in a period specified by reference data. The central processing unit receives the clock signal from the clock signal circuit and operates in accordance with the clock signal. The flash memory stores data which is electrically erased during an erase operation. The erase operation is executed during an erase time which includes a number of cycles of the clock signal calculated by the central processing unit. The central processing unit calculates a time for one cycle of the clock signal as a function of the period specified by the reference data and the number of cycles counted by the measuring unit.

Abstract: A single chip data processing apparatus having a central processing unit (CPU) and a flash memory constituted by electrically rewritable nonvolatile memory cells. The flash memory can be written with data under the control of the built-in CPU in an external write operation mode of the apparatus and, also, the CPU executes a data processing operation in accordance with a data processing program in a normal operation mode. In the external write operation mode, the CPU decodes a command by executing a command analyzing program so as to determine a process to be performed to the flash memory.

Abstract: A single chip semiconductor integrated circuit device having a central processing unit (CPU) and a flash memory which stores data to be processed by the CPU and which provides data to the CPU through the data bus in response to accessing instructions from the CPU through the address bus. The flash memory is constituted by a plurality of memory arrays in which a plurality of word lines are commonly employed for all of the memory arrays and a plurality of data lines are distributed amongst the memory arrays. The nonvolatile memory cells are arranged in a manner in which plural memory blocks are formed. The memory blocks formed can be facilitated with different memory capacities. This is achieved by having one or more rows of memory cells associated with one or more word lines provided within a memory block.

Abstract: A data processing apparatus having a built-in flash memory and being capable of performing a rewriting operation of the built-in flash memory, by use of versatilely used PROM writer, has a CPU, an electrically rewritable nonvolatile flash memory both formed in a single semiconductor substrate, and is operable in a mode in which the built-in flash memory is rewritable in accordance with commands supplied from a PROM writer. The data processing apparatus has a command latch which is externally writable when the above-mentioned operation mode is established, a command analyzer, that is, a command decoder, and a sequence controller for controlling a sequence of a rewriting operation of the flash memory in accordance with the decoded output of the command analyzer. The command analyzer and sequence controller may be realized by the CPU.

Abstract: An electrically rewritable flash memory device which has a memory cell array arranged in rows and columns of memory cells and which is divided into a plurality of memory blocks having different memory capacities. Each memory block having one or more rows of memory cells. A common voltage control circuit is provided for each of the memory blocks for applying a first potential to a common conductor for a memory block containing a memory cell selected with a selection voltage applied to its associated data line conductor for a writing operation and a second potential higher than the first potential to a common conductor for a memory block containing a memory cell unselected with the selection voltage applied to its associated data line conductor and containing no selected memory cell for a writing operation.