Abstract: An intake device of an engine comprises an intercooler, an intake passage including a downstream-side intake passage, and an EGR passage recirculating exhaust gas to the downstream-side intake passage. An intake-air supply opening having an opening area smaller than an area of a downstream-side face of an intercooler core is provided at a downstream side wall of a chamber. The downstream-side intake passage includes an extension passage portion extending upwardly along the downstream side wall. The intake-air supply opening includes an upper edge portion which separates the intake air flowing from an inside wall face of the extension passage portion and forms flowing main streams of the intake air inside the extension passage portion. EGR introduction ports are arranged at positions capable of supplying the EGR gas toward the flowing main streams.

Abstract: A determination is made whether or not the condition that the amount V of condensed water remaining in an intake passage has exceeded a predetermined upper limit has been met, based on an input parameter associated with the amount V. If, during an engine operation in an unsupercharged mode, a determination is made that the condition has been met, a condensed water discharging operation of a supercharger is performed such that the condensed water remaining is discharged to a cylinder of the engine through operation of the supercharger.

Abstract: An EGR system comprising at least one of an EGR cooler and an EGR valve is arranged above an intake manifold. A pair of facing surfaces which face each other with a space are provided at the EGR system attached to the intake manifold and the intake manifold. A damper plate having elasticity is arranged between these facing surfaces. The damper plate is configured to have a larger thickness than the above-described space and have a smaller Young's modulus than each of a lower-side facing-surface portion and an upper-side facing-surface portion, and the damper plate is clamped between the lower-side facing-surface portion and the upper-side facing-surface portion.

Abstract: An intake device of an engine comprises an intercooler, an intake passage including a downstream-side intake passage, and an EGR passage recirculating exhaust gas to the downstream-side intake passage. An intake-air supply opening having an opening area smaller than an area of a downstream-side face of an intercooler core is provided at a downstream side wall of a chamber. The downstream-side intake passage includes an extension passage portion extending upwardly along the downstream side wall. The intake-air supply opening includes an upper edge portion which separates the intake air flowing from an inside wall face of the extension passage portion and forms flowing main streams of the intake air inside the extension passage portion. EGR introduction ports are arranged at positions capable of supplying the EGR gas toward the flowing main streams.

Abstract: The present disclosure aims to improve circulation of intake air and distribution of bypass intake air to cylinders, while reducing an increase in the overall height of an engine. A supercharger extends along a cylinder bank at a side of a surge tank extending along the cylinder bank. A bypass pipe branching off from an upstream intake pipe configured to introduce the intake air into the supercharger extends along the cylinder bank above the supercharger. A downstream side intake pipe configured to guide the intake air from the supercharger to the surge tank extends downward from the supercharger. The downstream intake pipe is, in a U-shape as viewed along the cylinder bank, connected to the surge tank.

Abstract: A semiconductor device (1) includes a drain region (14) of a first conductivity type which includes a high-concentration drain region (14a), a first drain drift-region (14b), and a second drain drift-region (14c) of the first conductivity type, a source region (15) of the first conductivity type, a body region (16) of a second conductivity type, a gate insulating film (12), a gate electrode (13), and an STI insulating film (11) formed on the drain region (14). The second drain drift-region (14c) is formed from a first position (11f) of the STI insulating film (11) which is away from a first corner portion (11a) by a distance (x1) in a direction of a second corner portion (11b).

Abstract: The present disclosure aims to improve circulation of intake air and distribution of bypass intake air to cylinders, while reducing an increase in the overall height of an engine. A supercharger extends along a cylinder bank at a side of a surge tank extending along the cylinder bank. A bypass pipe branching off from an upstream intake pipe configured to introduce the intake air into the supercharger extends along the cylinder bank above the supercharger. A downstream side intake pipe configured to guide the intake air from the supercharger to the surge tank extends downward from the supercharger. The downstream intake pipe is, in a U-shape as viewed along the cylinder bank, connected to the surge tank.

Abstract: A determination is made whether or not the condition that the amount V of condensed water remaining in an intake passage has exceeded a predetermined upper limit has been met, based on an input parameter associated with the amount V. If, during an engine operation in an unsupercharged mode, a determination is made that the condition has been met, a condensed water discharging operation of a supercharger is performed such that the condensed water remaining is discharged to a cylinder of the engine through operation of the supercharger.

Abstract: A semiconductor device (1) includes a drain region (14) of a first conductivity type which includes a high-concentration drain region (14a), a first drain drift-region (14b), and a second drain drift-region (14c) of the first conductivity type, a source region (15) of the first conductivity type, a body region (16) of a second conductivity type, a gate insulating film (12), a gate electrode (13), and an STI insulating film (11) formed on the drain region (14). The second drain drift-region (14c) is formed from a first position (11f) of the STI insulating film (11) which is away from a first corner portion (11a) by a distance (x1) in a direction of a second corner portion (11b).

Abstract: Cell power supply lines are arranged for memory cell columns, and adjust impedances or voltage levels of the cell power supply lines according to the voltage levels of bit lines in the corresponding columns, respectively. In the data write operation, the cell power supply line is forced into a floating state according to the bit line potential on a selected column and has the voltage level changed, and a latching capability of a selected memory cell is reduced to write data fast. Even with a low power supply voltage, a static semiconductor memory device that can stably perform write and read of data is implemented.

Abstract: To suppress performance degradation of a semiconductor device, when the width of a first active region having a first field effect transistor formed therein is smaller than the width of a second active region having a second field effect transistor formed therein, the height of a surface of a first raised source layer of the first field effect transistor is made larger than the height of a surface of a second raised source layer of the second field effect transistor. Moreover, the height of a first surface of a raised drain layer of the first field effect transistor is made larger than a surface of a second raised drain layer of the second field effect transistor.

Abstract: Cell power supply lines are arranged for memory cell columns, and adjust impedances or voltage levels of the cell power supply lines according to the voltage levels of bit lines in the corresponding columns, respectively. In the data write operation, the cell power supply line is forced into a floating state according to the bit line potential on a selected column and has the voltage level changed, and a latching capability of a selected memory cell is reduced to write data fast. Even with a low power supply voltage, a static semiconductor memory device that can stably perform write and read of data is implemented.

Abstract: Cell power supply lines are arranged for memory cell columns, and adjust impedances or voltage levels of the cell power supply lines according to the voltage levels of bit lines in the corresponding columns, respectively. In the data write operation, the cell power supply line is forced into a floating state according to the bit line potential on a selected column and has the voltage level changed, and a latching capability of a selected memory cell is reduced to write data fast. Even with a low power supply voltage, a static semiconductor memory device that can stably perform write and read of data is implemented.

Abstract: Cell power supply lines are arranged for memory cell columns, and adjust impedances or voltage levels of the cell power supply lines according to the voltage levels of bit lines in the corresponding columns, respectively. In the data write operation, the cell power supply line is forced into a floating state according to the bit line potential on a selected column and has the voltage level changed, and a latching capability of a selected memory cell is reduced to write data fast. Even with a low power supply voltage, a static semiconductor memory device that can stably perform write and read of data is implemented.

Abstract: Cell power supply lines are arranged for memory cell columns, and adjust impedances or voltage levels of the cell power supply lines according to the voltage levels of bit lines in the corresponding columns, respectively. In the data write operation, the cell power supply line is forced into a floating state according to the bit line potential on a selected column and has the voltage level changed, and a latching capability of a selected memory cell is reduced to write data fast. Even with a low power supply voltage, a static semiconductor memory device that can stably perform write and read of data is implemented.

Abstract: Cell power supply lines are arranged for memory cell columns, and adjust impedances or voltage levels of the cell power supply lines according to the voltage levels of bit lines in the corresponding columns, respectively. In the data write operation, the cell power supply line is forced into a floating state according to the bit line potential on a selected column and has the voltage level changed, and a latching capability of a selected memory cell is reduced to write data fast. Even with a low power supply voltage, a static semiconductor memory device that can stably perform write and read of data is implemented.

Abstract: An object of the present invention is to provide a semiconductor device having a fin-type transistor that is excellent in characteristics by forming a fin-shaped semiconductor portion and a gate electrode with high precision or by making improvement regarding variations in characteristics among elements. The present invention is a semiconductor device including a fin-shaped semiconductor portion having a source region formed on one side thereof and a drain region formed on the other side thereof, and a gate electrode formed between the source region and the drain region to surround the fin-shaped semiconductor portion with a gate insulating film interposed therebetween. One solution for solving the problem according to the invention is that the gate electrode uses a metal material or a silicide material that is wet etchable.

Abstract: Cell power supply lines are arranged for memory cell columns, and adjust impedances or voltage levels of the cell power supply lines according to the voltage levels of bit lines in the corresponding columns, respectively. In the data write operation, the cell power supply line is forced into a floating state according to the bit line potential on a selected column and has the voltage level changed, and a latching capability of a selected memory cell is reduced to write data fast. Even with a low power supply voltage, a static semiconductor memory device that can stably perform write and read of data is implemented.

Abstract: In an SOI substrate having a semiconductor layer formed on the semiconductor substrate via an insulating layer, a MISFET is formed in each of the semiconductor layer in an nMIS formation region and a pMIS formation region. In power feeding regions, the semiconductor layer and the insulating layer are removed. In the semiconductor substrate, a p-type semiconductor region is formed so as to include the nMIS formation region and one of the power feeding regions, and an n-type semiconductor region is formed so as to include a pMIS formation region and the other one of the power feeding regions. In the semiconductor substrate, a p-type well having lower impurity concentration than the p-type semiconductor region is formed so as to contain the p-type semiconductor region, and an n-type well having lower impurity concentration than the n-type semiconductor region is formed so as to contain the n-type semiconductor region.

Abstract: An object of the present invention is to provide a semiconductor device having a fin-type transistor that is excellent in characteristics by forming a fin-shaped semiconductor portion and a gate electrode with high precision or by making improvement regarding variations in characteristics among elements. The present invention is a semiconductor device including a fin-shaped semiconductor portion having a source region formed on one side thereof and a drain region formed on the other side thereof, and a gate electrode formed between the source region and the drain region to surround the fin-shaped semiconductor portion with a gate insulating film interposed therebetween. One solution for solving the problem according to the invention is that the gate electrode uses a metal material or a silicide material that is wet etchable.