Patents by Inventor Hirofumi Shinohara

Hirofumi Shinohara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10900411
    Abstract: The present disclosure aims to improve circulation of intake air and distribution of bypass intake air to cylinders, while reducing an increase in the overall height of an engine. A supercharger extends along a cylinder bank at a side of a surge tank extending along the cylinder bank. A bypass pipe branching off from an upstream intake pipe configured to introduce the intake air into the supercharger extends along the cylinder bank above the supercharger. A downstream side intake pipe configured to guide the intake air from the supercharger to the surge tank extends downward from the supercharger. The downstream intake pipe is, in a U-shape as viewed along the cylinder bank, connected to the surge tank.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: January 26, 2021
    Assignee: Mazda Motor Corporation
    Inventors: Ken Yoshida, Ryotaro Nishida, Hidesaku Ebesu, Mitsunori Wasada, Mitsutaka Yamaya, Hisayuki Yamane, Yoshihiro Hamazume, Shuhei Tsujita, Hirofumi Shinohara, Eiji Takano, Tatsuya Koga, Tsukasa Hoshino, Masafumi Nakano, Kouichi Shimizu, Jiro Kato, Taketoshi Yamauchi
  • Patent number: 10886400
    Abstract: A semiconductor device (1) includes a drain region (14) of a first conductivity type which includes a high-concentration drain region (14a), a first drain drift-region (14b), and a second drain drift-region (14c) of the first conductivity type, a source region (15) of the first conductivity type, a body region (16) of a second conductivity type, a gate insulating film (12), a gate electrode (13), and an STI insulating film (11) formed on the drain region (14). The second drain drift-region (14c) is formed from a first position (11f) of the STI insulating film (11) which is away from a first corner portion (11a) by a distance (x1) in a direction of a second corner portion (11b).
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: January 5, 2021
    Assignee: ABLIC INC.
    Inventor: Hirofumi Shinohara
  • Publication number: 20200381245
    Abstract: A substrate processing method includes a first cleaning process and a second cleaning process. In the first cleaning process, a substrate is cleaned with a first cleaning solution. In the second cleaning process, the substrate is cleaned with a second cleaning solution having a lower cleanliness than the first cleaning solution after the first cleaning process.
    Type: Application
    Filed: May 22, 2020
    Publication date: December 3, 2020
    Inventors: Hirofumi Takeguchi, Kazuyoshi Shinohara, Takahisa Otsuka, Suguen Lee
  • Publication number: 20200370467
    Abstract: The present disclosure aims to improve circulation of intake air and distribution of bypass intake air to cylinders, while reducing an increase in the overall height of an engine. A supercharger extends along a cylinder bank at a side of a surge tank extending along the cylinder bank. A bypass pipe branching off from an upstream intake pipe configured to introduce the intake air into the supercharger extends along the cylinder bank above the supercharger. A downstream side intake pipe configured to guide the intake air from the supercharger to the surge tank extends downward from the supercharger. The downstream intake pipe is, in a U-shape as viewed along the cylinder bank, connected to the surge tank.
    Type: Application
    Filed: August 25, 2017
    Publication date: November 26, 2020
    Inventors: Ken Yoshida, Ryotaro Nishida, Hidesaku Ebesu, Mitsunori Wasada, Mitsutaka Yamaya, Hisayuki Yamane, Yoshihiro Hamazume, Shuhei Tsujita, Hirofumi Shinohara, Eiji Takano, Tatsuya Koga, Tsukasa Hoshino, Masafumi Nakano, Kouichi Shimizu, Jiro Kato, Taketoshi Yamauchi
  • Publication number: 20200370468
    Abstract: A determination is made whether or not the condition that the amount V of condensed water remaining in an intake passage has exceeded a predetermined upper limit has been met, based on an input parameter associated with the amount V. If, during an engine operation in an unsupercharged mode, a determination is made that the condition has been met, a condensed water discharging operation of a supercharger is performed such that the condensed water remaining is discharged to a cylinder of the engine through operation of the supercharger.
    Type: Application
    Filed: October 12, 2018
    Publication date: November 26, 2020
    Inventors: Kouichi SHIMIZU, Tsukasa HOSHINO, Ken YOSHIDA, Hirofumi SHINOHARA
  • Publication number: 20200281951
    Abstract: A heterocyclic compound represented by the general formula (1) or a salt thereof: wherein m, l, and n respectively represent an integer of 1 or 2; X represents —O— or —CH2—; R1 represents hydrogen, a lower alkyl group, a hydroxy-lower alkyl group, a protecting group, or a tri-lower alkylsilyloxy-lower alkyl group; R2 and R3, which are the same or different, each independently represent hydrogen or a lower alkyl group; or R2 and R3 are bonded to form a cyclo-C3-C8 alkyl group; and R4 represents an aromatic group or a heterocyclic group, wherein the aromatic or heterocyclic group may have one or more arbitrary substituent(s).
    Type: Application
    Filed: March 16, 2020
    Publication date: September 10, 2020
    Applicant: OTSUKA PHARMACEUTICAL CO., LTD.
    Inventors: Nobuaki ITO, Hirofumi SASAKI, Kuninori TAI, Tomoichi SHINOHARA
  • Patent number: 10697189
    Abstract: A connector for temporary scaffolding at an end of a lateral member, to be wedge-connected to a receiver around a strut, includes: a wedge body provided movably at the end of the lateral member upward and downward relative to the lateral member; a locking body including a claw formed such that, as a result of the wedge-body's moving downward, the claw could travel from initial to locking position with respect to the receiver; and a biasing body capable of pressing the locking body toward the wedge body, wherein the wedge body includes a shoulder protruding toward the locking body, the locking body includes an interfering portion protruding toward the wedge body, and when the claw is at the initial position, the shoulder is blocked by the interfering portion from moving upward, thereby preventing the wedge body from moving upward and the locking body from traveling toward the biasing body.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: June 30, 2020
    Assignee: NIKKEN LEASE KOGYO CO., LTD.
    Inventors: Tadakatsu Sekiyama, Tetsuro Okada, Sohei Wada, Masaki Ito, Hirofumi Sasaki, Shinobu Sato, Hazuki Shinohara
  • Patent number: 10603331
    Abstract: A heterocyclic compound represented by the general formula (1) or a salt thereof: wherein m, l, and n respectively represent an integer of 1 or 2; X represents —O— or —CH2—; R1 represents hydrogen, a lower alkyl group, a hydroxy-lower alkyl group, a protecting group, or a tri-lower alkylsilyloxy-lower alkyl group; R2 and R3, which are the same or different, each independently represent hydrogen or a lower alkyl group; or R2 and R3 are bonded to form a cyclo-C3-C8 alkyl group; and R4 represents an aromatic group or a heterocyclic group, wherein the aromatic or heterocyclic group may have one or more arbitrary substituent(s).
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: March 31, 2020
    Assignee: Otsuka Pharmaceutical Co., Ltd.
    Inventors: Nobuaki Ito, Hirofumi Sasaki, Kuninori Tai, Tomoichi Shinohara
  • Publication number: 20190378925
    Abstract: A semiconductor device (1) includes a drain region (14) of a first conductivity type which includes a high-concentration drain region (14a), a first drain drift-region (14b), and a second drain drift-region (14c) of the first conductivity type, a source region (15) of the first conductivity type, a body region (16) of a second conductivity type, a gate insulating film (12), a gate electrode (13), and an STI insulating film (11) formed on the drain region (14). The second drain drift-region (14c) is formed from a first position (11f) of the STI insulating film (11) which is away from a first corner portion (11a) by a distance (x1) in a direction of a second corner portion (11b).
    Type: Application
    Filed: June 5, 2019
    Publication date: December 12, 2019
    Inventor: Hirofumi SHINOHARA
  • Publication number: 20190345725
    Abstract: A connector for temporary scaffolding at an end of a lateral member, to be wedge-connected to a receiver around a strut, includes: a wedge body provided movably at the end of the lateral member upward and downward relative to the lateral member; a locking body including a claw formed such that, as a result of the wedge-body's moving downward, the claw could travel from initial to locking position with respect to the receiver; and a biasing body capable of pressing the locking body toward the wedge body, wherein the wedge body includes a shoulder protruding toward the locking body, the locking body includes an interfering portion protruding toward the wedge body, and when the claw is at the initial position, the shoulder is blocked by the interfering portion from moving upward, thereby preventing the wedge body from moving upward and the locking body from traveling toward the biasing body.
    Type: Application
    Filed: July 25, 2019
    Publication date: November 14, 2019
    Applicant: NIKKEN LEASE KOGYO CO., LTD.
    Inventors: Tadakatsu SEKIYAMA, Tetsuro OKADA, Sohei WADA, Masaki ITO, Hirofumi SASAKI, Shinobu SATO, Hazuki SHINOHARA
  • Publication number: 20190142852
    Abstract: A heterocyclic compound represented by the general formula (1) or a salt thereof: wherein m, l, and n respectively represent an integer of 1 or 2; X represents —O— or —CH2—; R1 represents hydrogen, a lower alkyl group, a hydroxy-lower alkyl group, a protecting group, or a tri-lower alkylsilyloxy-lower alkyl group; R2 and R3, which are the same or different, each independently represent hydrogen or a lower alkyl group; or R2 and R3 are bonded to form a cyclo-C3-C8 alkyl group; and R4 represents an aromatic group or a heterocyclic group, wherein the aromatic or heterocyclic group may have one or more arbitrary substituent(s).
    Type: Application
    Filed: August 30, 2018
    Publication date: May 16, 2019
    Applicant: OTSUKA PHARMACEUTICAL CO., LTD.
    Inventors: Nobuaki ITO, Hirofumi SASAKI, Kuninori TAI, Tomoichi SHINOHARA
  • Patent number: 10242733
    Abstract: Cell power supply lines are arranged for memory cell columns, and adjust impedances or voltage levels of the cell power supply lines according to the voltage levels of bit lines in the corresponding columns, respectively. In the data write operation, the cell power supply line is forced into a floating state according to the bit line potential on a selected column and has the voltage level changed, and a latching capability of a selected memory cell is reduced to write data fast. Even with a low power supply voltage, a static semiconductor memory device that can stably perform write and read of data is implemented.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: March 26, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Koji Nii, Shigeki Obayashi, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara
  • Patent number: 10121705
    Abstract: To suppress performance degradation of a semiconductor device, when the width of a first active region having a first field effect transistor formed therein is smaller than the width of a second active region having a second field effect transistor formed therein, the height of a surface of a first raised source layer of the first field effect transistor is made larger than the height of a surface of a second raised source layer of the second field effect transistor. Moreover, the height of a first surface of a raised drain layer of the first field effect transistor is made larger than a surface of a second raised drain layer of the second field effect transistor.
    Type: Grant
    Filed: August 27, 2014
    Date of Patent: November 6, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hirofumi Shinohara, Hidekazu Oda, Toshiaki Iwamatsu
  • Publication number: 20180247692
    Abstract: Cell power supply lines are arranged for memory cell columns, and adjust impedances or voltage levels of the cell power supply lines according to the voltage levels of bit lines in the corresponding columns, respectively. In the data write operation, the cell power supply line is forced into a floating state according to the bit line potential on a selected column and has the voltage level changed, and a latching capability of a selected memory cell is reduced to write data fast. Even with a low power supply voltage, a static semiconductor memory device that can stably perform write and read of data is implemented.
    Type: Application
    Filed: April 27, 2018
    Publication date: August 30, 2018
    Inventors: Koji NII, Shigeki OBAYASHI, Hiroshi MAKINO, Koichiro ISHIBASHI, Hirofumi SHINOHARA
  • Patent number: 9984744
    Abstract: Cell power supply lines are arranged for memory cell columns, and adjust impedances or voltage levels of the cell power supply lines according to the voltage levels of bit lines in the corresponding columns, respectively. In the data write operation, the cell power supply line is forced into a floating state according to the bit line potential on a selected column and has the voltage level changed, and a latching capability of a selected memory cell is reduced to write data fast. Even with a low power supply voltage, a static semiconductor memory device that can stably perform write and read of data is implemented.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: May 29, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Koji Nii, Shigeki Obayashi, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara
  • Publication number: 20170345488
    Abstract: Cell power supply lines are arranged for memory cell columns, and adjust impedances or voltage levels of the cell power supply lines according to the voltage levels of bit lines in the corresponding columns, respectively. In the data write operation, the cell power supply line is forced into a floating state according to the bit line potential on a selected column and has the voltage level changed, and a latching capability of a selected memory cell is reduced to write data fast. Even with a low power supply voltage, a static semiconductor memory device that can stably perform write and read of data is implemented.
    Type: Application
    Filed: August 18, 2017
    Publication date: November 30, 2017
    Inventors: Koji NII, Shigeki OBAYASHI, Hiroshi MAKINO, Koichiro ISHIBASHI, Hirofumi SHINOHARA
  • Patent number: 9767893
    Abstract: Cell power supply lines are arranged for memory cell columns, and adjust impedances or voltage levels of the cell power supply lines according to the voltage levels of bit lines in the corresponding columns, respectively. In the data write operation, the cell power supply line is forced into a floating state according to the bit line potential on a selected column and has the voltage level changed, and a latching capability of a selected memory cell is reduced to write data fast. Even with a low power supply voltage, a static semiconductor memory device that can stably perform write and read of data is implemented.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: September 19, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Koji Nii, Shigeki Obayashi, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara
  • Publication number: 20170011794
    Abstract: Cell power supply lines are arranged for memory cell columns, and adjust impedances or voltage levels of the cell power supply lines according to the voltage levels of bit lines in the corresponding columns, respectively. In the data write operation, the cell power supply line is forced into a floating state according to the bit line potential on a selected column and has the voltage level changed, and a latching capability of a selected memory cell is reduced to write data fast. Even with a low power supply voltage, a static semiconductor memory device that can stably perform write and read of data is implemented.
    Type: Application
    Filed: September 23, 2016
    Publication date: January 12, 2017
    Inventors: Koji NII, Shigeki OBAYASHI, Hiroshi MAKINO, Koichiro ISHIBASHI, Hirofumi SHINOHARA
  • Patent number: 9515170
    Abstract: An object of the present invention is to provide a semiconductor device having a fin-type transistor that is excellent in characteristics by forming a fin-shaped semiconductor portion and a gate electrode with high precision or by making improvement regarding variations in characteristics among elements. The present invention is a semiconductor device including a fin-shaped semiconductor portion having a source region formed on one side thereof and a drain region formed on the other side thereof, and a gate electrode formed between the source region and the drain region to surround the fin-shaped semiconductor portion with a gate insulating film interposed therebetween. One solution for solving the problem according to the invention is that the gate electrode uses a metal material or a silicide material that is wet etchable.
    Type: Grant
    Filed: February 5, 2016
    Date of Patent: December 6, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Toshiaki Iwamatsu, Takashi Terada, Hirofumi Shinohara, Kozo Ishikawa, Ryuta Tsuchiya, Kiyoshi Hayashi
  • Patent number: 9496028
    Abstract: Cell power supply lines are arranged for memory cell columns, and adjust impedances or voltage levels of the cell power supply lines according to the voltage levels of bit lines in the corresponding columns, respectively. In the data write operation, the cell power supply line is forced into a floating state according to the bit line potential on a selected column and has the voltage level changed, and a latching capability of a selected memory cell is reduced to write data fast. Even with a low power supply voltage, a static semiconductor memory device that can stably perform write and read of data is implemented.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: November 15, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Koji Nii, Shigeki Obayashi, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara