Abstract: A semiconductor memory device (1) comprises a normal RAM (2) and a redundancy RAM (3) provided independently from the normal RAM (2), serving as a redundancy circuit, and a control unit (4) for replacing a normal memory cell array of the normal RM (2) by a redundancy memory call array of the redundancy RAM (3). The control unit (4) can replace the normal memory cell array by some of a plurality of redundancy memory cells constituting the redundancy memory cell array. Therefore, a defective normal memory cell array can be replaced with using a redundancy memory cell which does not have a defect. As a result, a manufacturing yield of the semiconductor memory device (1) can be improved. With this constitution provided is a technique to improve the manufacturing yield of a semiconductor memory device which comprises a redundancy circuit.

Abstract: A semiconductor device, wherein the lowering, in comparison with a background art, of the resistance of a source line is achieved and a manufacturing method for the same are obtained. A protruding portion (2m) that protrudes in the Y direction towards each drain region (3m) from a trunk portion (1) is formed in a source line (SLa) in each of five memory cells corresponding to “1” of the ROM code from among eight memory cells belonging to the m-th row. In the same manner, a protruding portion (2n) that protrudes in the Y direction towards each drain region (3n) from the trunk portion (1) is formed in the source line (SLa) in each of four memory cells corresponding to “1” of the ROM code from among eight memory cells belonging to the n-th row.

Abstract: A semiconductor memory device (1) comprises a normal RAM (2) and a redundancy RAM (3) provided independently from the normal RAM (2), serving as a redundancy circuit, and a control unit (4) for replacing a normal memory cell array of the normal RAM (2) by a redundancy memory cell array of the redundancy RAM (3). The control unit (4) can replace the normal memory cell array by some of a plurality of redundancy memory cells constituting the redundancy memory cell array. Therefore, without using a redundancy memory cell which has a defect, a defective normal memory cell array can be replaced. As a result, a manufacturing yield of the semiconductor memory device (1) can be improved. With this constitution provided is a technique to improve the manufacturing yield of a semiconductor memory device which comprises a redundancy circuit.

Abstract: A semiconductor device, wherein the lowering, in comparison with a background art, of the resistance of a source line is achieved and a manufacturing method for the same are obtained.

Abstract: Wiring between output terminals of a source driver IC (output terminals of a TCP for source driver IC) and picture elements is equalized when number of the picture elements is not an integer multiplied by number of outputs of the source driver IC in the liquid crystal display. By giving a start pulse for indicating a start timing of drive sections to a predetermined drive section at a timing different from an originally set start timing, a part of output terminals of the drive section is made unavailable.

Abstract: A semiconductor memory includes a redundant RAM disposed independently of at least one regular RAM, the redundant RAM having redundant memory elements by which defective memory elements of the regular RAM can be replaced, and a control block for selecting either at least the regular RAM or the redundant RAM according to an address applied thereto, and for reading data from a memory cell of the selected RAM specified by the address. A plurality of regular RAMs can be disposed and the redundant RAM includes redundant memory elements by which defective memory elements of an arbitrary one of the plurality of regular RAMs can be replaced. The control block selects either one of the plurality of regular RAMs or the redundant RAM according to an address applied thereto, and reads data from a memory cell of the selected RAM specified by the address.

Abstract: Wiring between output terminals of a source driver IC (output terminals of a TCP for source driver IC) and picture elements is equalized when number of the picture elements is not an integer multiplied by number of outputs of the source driver IC in the liquid crystal display. By giving a start pulse for indicating a start timing of drive sections to a predetermined drive section at a timing different from an originally set start timing, a part of output terminals of the drive section is made unavailable.

Abstract: A control circuit for controlling a driving circuit that provides signals to a displaying means, wherein a function of outputting a plurality of digital signals at different phases is included, and said phases can be set by selective elements.

Abstract: A manufacturing method for a semiconductor device permits a MOSFET with a pocket layer to be securely formed even when microminiaturization makes it difficult to implant impurity ions at an angle with respect to a silicon substrate in manufacturing a semiconductor, a MOSFET having a pocket layer in particular. A gate electrode composed of a gate oxide film, a poly-silicon, and a tungsten silicide, and a nitride film pattern are selectively formed on a p-type silicon substrate, then p-type impurity ions are implanted perpendicularly to the p-type silicon substrate. A p-type ion implantation region formed by implanting the p-type impurity ions is diffused for activation to thereby form a pocket layer before another ion implantation region is formed.

Abstract: A semiconductor integrated circuit device electrically simulating a vital neural network includes neuron units. Each neuron unit includes a plurality of laterally connected synapse units, an accumulator for accumulatively adding the outputs of the final synapse unit in the lateral connection, and a nonlinear processor for carrying out a predetermined nonlinear operational processing on the output of the accumulator. The number of the neuron units and the number of synapse units per neuron unit satisfy a relation of an integer multiple. The number of regularly operating neuron units can be made equal to that of the synapse units per neuron unit, whereby it is possible to prevent the neuron units from performing meaningless operations and an efficient neural network can be obtained.

Abstract: A module cell generating device of a semiconductor integrated circuit includes a parameter input part for applying a designation parameter, a basic cell group storing the basic cells, and a basic cell arranging and wiring process part for generating layout designing data by utilizing a structure description part which is a control description for defining the arrangement method and the wiring method of the basic cells, the designation parameter, the structure description, and the basic cells. Furthermore, it includes a basic cell generating process part for generating the newly designated basic cells in accordance with the designation parameter.

Abstract: Memory cell array includes a plurality of 2-port memory cells. A first row address decoder for decoding a first address signal to select a first word line included in any one of a plurality of word line groups, and a second row address decoder for decoding a second address signal to select a second word line included in any one of a plurality of word line groups are provided. A word line driving circuit receives output signals of first and second row address decoders to drive first and second word lines in accordance with a predetermined inhibit condition.

Abstract: A design verification device includes a diagram data memory for storing designed diagram data, a design reference value memory for storing a design reference value, a determination circuit for making determination with different weight between intersecting directions of a diagram to either the distance or the design reference value in calculating the distance between diagram data provided from the diagram data memory means for making determination whether the calculated distance follows the design reference value; and an error signal output circuit for providing an error signal when determination is made that the design reference value is not followed by the determination circuit.

Abstract: A semiconductor logic circuit apparatus which include a first switching element consisting of a field effect transistor for changing holding data, an inverter circuit whose input is connected with one end of the first switching element, a feedback circuit whose input and output are connected with the output and input of the inverter circuit, and a second switching element connected between the output of the feedback circuit and first or second potential. The second switching element is effective for enabling and disabling the feedback circuit.The first and second switching elements are opened/closed in reverse phase to each other. Feedback of the feedback circuit is prevented until the inverter circuit is driven from its "0" to its "1" holding state, so that driving of the inverter circuit becomes easy and operational stability and operating speed are enhanced.

Abstract: A semiconductor memory device includes a plurality of ports enabling simultaneous writing and reading of data of M words.times.N bits. A plurality of memory cells are arranged in (M/n) rows.times.(n.times.N) columns in a memory call array, write and read word lines are commonly connected to the memory cells of one row, and write column selecting line are connected to every n (the number of words) memory cells of the memory cells of one row. Write and read bit lines are connected to the memory cells of one column. Data is input to the write bit line from an input terminal through a write circuit. and data read from the memory cell is output to an output terminal through a sense amplifier. A first port is formed by the write word lines, the write column selecting lines, the write bit lines and the input terminal, and a second port is formed by the read word lines, read bit lines and the output terminal. M, N and n are natural numbers and M, N.gtoreq.n.

Abstract: A semiconductor memory device has multiple ports for enabling writing and reading of data simultaneously. A memory cell array comprises a plurality of memory cells (1) arranged in rows and in columns, write and read word lines (WW, RW) being connected to the memory cells of the respective rows and write and read bit lines (WB, RB) being connected to the memory cells of the respective columns. Data is inputted to the write bit lines (WB) from an input terminal (DI) through a write circuit (3i) and data read out form the corresponding memory cells are outputted to an output terminal (DO) through a sense amplifier (4i). A first port is formed by the write word line, the write bit line and the input terminal, while a second part is formed by the read word line, the read bit line and the output terminal.

Abstract: In a content addressable memory (CAM) cell according to the present invention, a pair of non-volatile memory transistors hold data, whereby stored data will not disappear even if power is cut. Conducting terminals of these non-volatile transistors are connected to a bit line pair, so that the stored data can be directly read out from the bit line pair. Further, the invention CAM system converts the value of a current flowing in a match line into a voltage value to perform content reference, and hence the same can be employed as an associative memory system.

Abstract: Test data stored in a data register 13a are applied to a data generator 11a and compared with a 1 bit signal stored in a scan latch 1c to determine the coincidence or non-coincidence therebetween. Outputs from the data generator 11a are applied to RAM 10 to be written in a designated region in a memory cell array 6. Data read from the said region of the memory cell array 6 are compared with expected value data in a comparator 12. Thus, the collation of data is carried out.

Abstract: A dynamic random access memory device includes a pair of write-in data transferring buses for transferring data to be written, a pair of read-out data transferring buses for transferring data to be read provided additionally and separately from the write-in data transferring bus pair and a plurality of current mirror type sense amplifiers formed of CMOS transistors and each amplifier being provided between a bit line pair and the read-out data transferring bus pair and having input nodes connected to the corresponding bit line pair and the read-out data transferring bus pair forming output nodes thereof. The current mirror type sense amplifiers of CMOS transistors are activated in response to an output of a column decoder at earlier time than the time when conventional flip-flop type sense amplifiers are activated.

Abstract: A memory matrix is segmented in the direction of columns into a plurality of groups of memory cells. The memory cells are accessible through respective preceding word lines each of which is provided for each of the rows of the matrix and commonly to all of the groups of the memory cells and group word lines each of which is provided per group and per row, so that a path for column current is set up during access time only in the column which belongs to a particular group including a particular memory to be accessed.