Patents by Inventor Hirofumi Uchida

Hirofumi Uchida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240091641
    Abstract: Methods and apparatus provide for acquiring position information about a head-mounted display; performing information processing using the position information about the head-mounted display; generating and outputting data of an image to be displayed as a result of the information processing; and generating and outputting data of an image of a user guide indicating position information about a user in a real space using the position information about the head-mounted display, where the image of the user guide represents a state of the real space in which the user is physically located, as viewed obliquely.
    Type: Application
    Filed: December 4, 2023
    Publication date: March 21, 2024
    Applicant: Sony Interactive Entertainment Inc.
    Inventors: Shoichi Ikenoue, Tatsuo Tsuchie, Tetsugo Inada, Masaki Uchida, Hirofumi Okamoto
  • Publication number: 20240071128
    Abstract: A detection device includes a plurality of optical sensors arranged in a detection area, a light source configured to emit light that is emitted to an object to be detected and is detected by the optical sensors, and a processor configured to perform processing based on outputs from the optical sensors. The processor is configured to determine, based on the outputs of the respective optical sensors obtained at a cycle of a predetermined period, an optical sensor an output of which is to be employed from among the optical sensors.
    Type: Application
    Filed: November 3, 2023
    Publication date: February 29, 2024
    Inventors: Hirofumi KATO, Makoto UCHIDA, Takanori TSUNASHIMA, Takashi NAKAMURA, Akio TAKIMOTO, Takao SOMEYA, Tomoyuki YOKOTA
  • Patent number: 11772301
    Abstract: A method of manufacturing a hexagonal Group-III nitride semiconductor plate crystal using a crystal cutting wire. where the hexagonal semiconductor crystal has one principal face on one side and another principal face on an opposite side, and the hexagonal semiconductor crystal is cut by causing the crystal cutting wire to move so as to (i) divide the one principal face and the another principal face and (ii) satisfy conditions of Expressions (A) and (B): 25°<??90°??Expression (A); and ?=90°±5°??Expression (B) where ? represents an angle formed by a c axis of the hexagonal Group-III nitride semiconductor crystal and a normal line of a crystal face cut out by the wire, and ? represents an angle formed by a reference axis, which is obtained by perpendicularly projecting the c axis of the hexagonal Group-III nitride semiconductor crystal to the crystal face cut out by the wire, and a cutting direction.
    Type: Grant
    Filed: January 27, 2021
    Date of Patent: October 3, 2023
    Assignee: Mitsubishi Chemical Corporation
    Inventors: Hirofumi Uchida, Yukio Okano
  • Publication number: 20210146575
    Abstract: A method of manufacturing a hexagonal Group-III nitride semiconductor plate crystal using a crystal cutting wire. where the hexagonal semiconductor crystal has one principal face on one side and another principal face on an opposite side, and the hexagonal semiconductor crystal is cut by causing the crystal cutting wire to move so as to (i) divide the one principal face and the another principal face and (ii) satisfy conditions of Expressions (A) and (B): 25°<??90°??Expression (A); and ?=90°±5°??Expression (B) where ? represents an angle formed by a c axis of the hexagonal Group-III nitride semiconductor crystal and a normal line of a crystal face cut out by the wire, and ? represents an angle formed by a reference axis, which is obtained by perpendicularly projecting the c axis of the hexagonal Group-III nitride semiconductor crystal to the crystal face cut out by the wire, and a cutting direction.
    Type: Application
    Filed: January 27, 2021
    Publication date: May 20, 2021
    Applicant: Mitsubishi Chemical Corporation
    Inventors: Hirofumi UCHIDA, Yukio OKANO
  • Patent number: 10370557
    Abstract: A radiation curable secondary coating composition for optical fiber is described and claimed. This radiation curable secondary coating composition includes component (A) which is a urethane (meth)acrylate and component (B) which is a (meth)acrylate compound with two or more ethylenically unsaturated groups and one or more bisphenol structures; wherein the content of component (B) in the composition is 60-300 mass parts per 100 mass parts of component (A). The liquid secondary coating has a viscosity at 25° C. of from about 0.1 Pa·s to about 15 Pa·s. Films obtained by curing the liquid radiation curable secondary coating composition of the present invention have a Young's modulus of from about 600 MPa to about 500 MPa and the breaking elongation of the cured film is from about to 5% to about 50%.
    Type: Grant
    Filed: November 18, 2015
    Date of Patent: August 6, 2019
    Assignee: DSM IP Assets B.V.
    Inventors: Hirofumi Uchida, Zen Komiya
  • Publication number: 20180079109
    Abstract: A plate crystal cut from a gallium nitride crystal with a crystal cutting wire, where the plate crystal has a principal face of (20?21), and a magnitude of warpage of the plate crystal is 1.0 ?m/mm or less in a line along the perpendicular projection of the c axis on the principal face passing through the center of the principal face.
    Type: Application
    Filed: November 29, 2017
    Publication date: March 22, 2018
    Inventors: Hirofumi UCHIDA, Yukio OKANO
  • Publication number: 20170355874
    Abstract: A radiation curable secondary coating composition for optical fiber is described and claimed. This radiation curable secondary coating composition includes component (A) which is a urethane (meth)acrylate and component (B) which is a (meth)acrylate compound with two or more ethylenically unsaturated groups and one or more bisphenol structures; wherein the content of component (B) in the composition is 60-300 mass parts per 100 mass parts of component (A). The liquid secondary coating has a viscosity at 25° C. of from about 0.1 Pa·s to about 15 Pa·s. Films obtained by curing the liquid radiation curable secondary coating composition of the present invention have a Young's modulus of from about 600 MPa to about 500 MPa and the breaking elongation of the cured film is from about to 5% to about 50%.
    Type: Application
    Filed: November 18, 2015
    Publication date: December 14, 2017
    Inventors: Hirofumi UCHIDA, Zen KOMIYA
  • Publication number: 20130284160
    Abstract: A method of efficiently manufacturing a hexagonal semiconductor plate crystal with small warpage is provided. The method of manufacturing a hexagonal semiconductor plate crystal is a method of manufacturing a hexagonal semiconductor plate crystal by cutting a hexagonal semiconductor crystal using a crystal cutting wire, wherein the hexagonal semiconductor crystal is cut by causing the crystal cutting wire to move relative to the hexagonal semiconductor crystal so as to satisfy the conditions of 25°<??90° and ?=90°±5° where ? represents an angle formed by the c axis of the hexagonal semiconductor crystal and the normal line of the crystal face cut out by the wire and ? represents an angle formed by a reference axis, which is obtained by perpendicularly projecting the c axis of the hexagonal semiconductor crystal to the crystal face cut out by the wire, and a cutting direction.
    Type: Application
    Filed: June 28, 2013
    Publication date: October 31, 2013
    Inventors: Hirofumi UCHIDA, Yukio OKANO
  • Publication number: 20130199818
    Abstract: The invention relates to a radiation curable resin composition for forming a coating layer for electrical wire; wherein the electrical wire is destined for use as automotive electrical wire. In addition, this invention relates to a radiation curable resin composition for forming a coating layer for telephone cable and electrical wire for connecting between electronic devices and inside electronic devices. The resin composition includes the following: (A) a urethane (meth)acrylate having a hard segment derived from an aromatic polyol and a soft segment derived from an aliphatic polyol in a single molecule; (B) a compound with a cyclic structure and one ethylenic unsaturated group; and (C) a radiation polymerization initiator.
    Type: Application
    Filed: July 21, 2011
    Publication date: August 8, 2013
    Applicant: DSM IP ASSETS B.V.
    Inventors: Hirofumi Uchida, Hirokazu Imai, Yuutoku Yamashita, Takahiko Kurosawa
  • Patent number: 8367204
    Abstract: A curable resin composition comprising an antioxidant, a UV absorber, and a (meth)acrylate oligomer comprising polyether units. Cured products made from the liquid curable resin composition of the present invention have excellent light stability. The resin composition is suitable as a coating material for optical fibers.
    Type: Grant
    Filed: October 23, 2001
    Date of Patent: February 5, 2013
    Assignees: DSM IP Assets B.V., JSR Corporation
    Inventors: Hirofumi Uchida, Zen Komiya, Takashi Ukachi
  • Patent number: 8178904
    Abstract: A gate array of a semiconductor substrate on which plural unit cells are arranged in parallel, the unit cells having the same pattern that includes a source potential region VDD, a PMOS, an NMOS and a ground potential region GND. Metal wiring lines being formed, with an insulating layer between, on the unit cells, with contacts that make electrical connection between the metal wiring lines and the unit cell transistors. The gate wiring of a transistor in a non-used unit cell is used in place of a metal wiring line. By doing so, the area of metal wiring lines in a gate array is reduced and the array wiring efficiency is increased.
    Type: Grant
    Filed: December 10, 2010
    Date of Patent: May 15, 2012
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Hirofumi Uchida
  • Patent number: 8063414
    Abstract: A standard cell, placed between a power rail and a ground rail in an integrated circuit, has active areas with connecting arms that extend beneath the power rail and ground rail. The connecting arms conduct current between the power and ground rails and the source regions of transistors in the active areas. The connecting arms include segments extending from these source regions to points beneath the power and ground rails, and segments running longitudinally beneath the power and ground rails. The connecting arms replace metal wiring that would otherwise be required, enabling the size of the standard cell to be reduced.
    Type: Grant
    Filed: April 23, 2007
    Date of Patent: November 22, 2011
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Hirofumi Uchida
  • Patent number: 8023796
    Abstract: A video signal producing system includes an imaging device for obtaining progressive imaging signals having various frame rates, a recording device for recording an output signal of the imaging device and a reproduction device for reproducing a recording signal obtained from the recording device. The imaging device includes a frame rate converting portion for converting the imaging signals to an output having a predetermined frame rate and the reproduction device changes a reproduction speed in response to each of the various frame rates so as to generate an output having a substantial number of frames such that the substantial number of the frames assumes a predetermined value.
    Type: Grant
    Filed: November 6, 2001
    Date of Patent: September 20, 2011
    Assignee: Panasonic Corporation
    Inventors: Ryoji Asada, Kazumasa Motoda, Shoji Nishikawa, Shigeru Awamoto, Shiro Kato, Hirofumi Uchida
  • Publication number: 20110073916
    Abstract: A gate array of a semiconductor substrate on which plural unit cells are arranged in parallel, the unit cells having the same pattern that includes a source potential region VDD, a PMOS, an NMOS and a ground potential region GND. Metal wiring lines being formed, with an insulating layer between, on the unit cells, with contacts that make electrical connection between the metal wiring lines and the unit cell transistors. The gate wiring of a transistor in a non-used unit cell is used in place of a metal wiring line. By doing so, the area of metal wiring lines in a gate array is reduced and the array wiring efficiency is increased.
    Type: Application
    Filed: December 10, 2010
    Publication date: March 31, 2011
    Applicant: OKI SEMICONDUCTOR CO., LTD.
    Inventor: Hirofumi Uchida
  • Patent number: 7875909
    Abstract: A gate array of a semiconductor substrate on which plural unit cells are arranged in parallel, the unit cells having the same pattern that includes a source potential region VDD, a PMOS, an NMOS and a ground potential region GND. Metal wiring lines being formed, with an insulating layer between, on the unit cells, with contacts that make electrical connection between the metal wiring lines and the unit cell transistors. The gate wiring of a transistor in a non-used unit cell is used in place of a metal wiring line. By doing so, the area of metal wiring lines in a gate array is reduced and the array wiring efficiency is increased.
    Type: Grant
    Filed: November 17, 2006
    Date of Patent: January 25, 2011
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Hirofumi Uchida
  • Patent number: 7863970
    Abstract: A current source device having a plurality of current output circuits each including a current output FET, first and second switch FETs respectively series-connected to source and drain sides of the current output FET to form a series circuit, a source voltage supply which applies a positive-side potential of a source voltage to the first switch FET and applies a negative-side potential of the source voltage to the second switch FET to supply the source voltage to the series circuit, and an output terminal connected between the current output FET and the second switch FET; and a gate voltage supply circuit which supplies a common gate voltage to the gates of the current output FETs, wherein each of the current output circuits further includes a third switch FET provided between the current output FET and the second switch FET.
    Type: Grant
    Filed: July 28, 2008
    Date of Patent: January 4, 2011
    Assignee: Oki Semiconductor Co., Ltd.
    Inventors: Hirofumi Uchida, Takashi Honda
  • Publication number: 20090091359
    Abstract: The present invention provides a current source device comprising a plurality of current output circuits each including a current output FET, first and second switch FETS respectively series-connected to source and drain sides of the current output FET to form a series circuit, source voltage supply means which applies a positive-side potential of a source voltage to the first switch FET and applies a negative-side potential of the source voltage to the second switch FET to supply the source voltage to the series circuit, and an output terminal connected between the current output FET and the second switch FET; and a gate voltage supply circuit which supplies a common gate voltage to the gates of the current output FETS, wherein each of the current output circuits further includes a third switch FET provided between the current output FET and the second switch FET.
    Type: Application
    Filed: July 28, 2008
    Publication date: April 9, 2009
    Applicant: OKI ELECTRIC INDUSTRY CO., LTD.
    Inventors: Hirofumi Uchida, Takashi Honda
  • Publication number: 20090052568
    Abstract: In a quadrature amplitude modulation (QAM) communication system and corresponding method, and a QAM receiving apparatus and corresponding method, a sending apparatus that generates a sending signal adds CRC bits thereto. In a receiving apparatus, data rate is determined without a 16QAM demapping circuit and/or notification of the data rate, by 64QAM demapping a symbol string based on the received signal using a demapping circuit, independently of whether 16QAM or 64QAM was used on the sent signal. A bit string is thus obtained, and by thinning the bit string responsive to a CRC detection result of a CRC detection circuit, an output signal is provided using a thinning circuit.
    Type: Application
    Filed: June 27, 2008
    Publication date: February 26, 2009
    Applicant: OKI ELECTRIC INDUSTRY CO., LTD.
    Inventors: Hirofumi Uchida, Takashi Honda
  • Patent number: 7400820
    Abstract: For conversion of a first video signal into a second video signal of a different format, a second auxiliary data packet is generated from a header carrying location data for multiplexing a first auxiliary data packet and main data of a first auxiliary data packet in the first video signal, and is multiplexed with the second video signal. For conversion from the second video signal into the first video signal, the first auxiliary data packet is generated from the header and the main data of the second auxiliary data packet, and multiplexed at the location determined by the location data in the first video signal.
    Type: Grant
    Filed: April 22, 2002
    Date of Patent: July 15, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hirofumi Uchida, Tatsushi Bannai
  • Patent number: 7385233
    Abstract: A gate array integrated circuit forming part of a semiconductor integrated circuit includes a basic layer of a unit cell in which a PMOS and an NMOS transistor are connected with a poly-silicon strip. The poly-silicon strip has gate terminal regions formed to laterally extend to allow two or more contact pads or through-holes to be disposed in each gate terminal region. It is thus possible to improve wiring efficiency and also micro-miniaturization and yield of the gate array integrated circuit. A layout method for a gate array integrated circuit is also provided.
    Type: Grant
    Filed: September 8, 2005
    Date of Patent: June 10, 2008
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Hirofumi Uchida