Patents by Inventor Hirofumi Yamashita

Hirofumi Yamashita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6928535
    Abstract: An image input section and a signal processing section are provided. The image input section includes an array of pixel in which a plurality of pixels having a CMOS type photoelectric converting element for converting incident light to an electric signal are arranged in a matrix, and a data read-out circuit having the same number of A/D converters as the number of the pixels arranged in one row of the array of pixel and serving to convert the analog signal converted by the pixels into a digital signal and to output the digital signal. The signal processing section includes plurality of processors. Each of the processors includes a plurality of processing elements (PE) provided on the A/D converter provided in the data read-out circuit by one to one. Moreover, a plurality of PEs provided in each of the processors have the same data processing function in the same processor. Furthermore, the PEs in the processor carry out a signal processing in parallel in response to an instruction.
    Type: Grant
    Filed: July 16, 2002
    Date of Patent: August 9, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hirofumi Yamashita, Charles G. Sodini
  • Publication number: 20050123109
    Abstract: In this invention, an apparatus of which the power supply is in the off state is remotely controlled through a communications network. Each of one or a plurality of controlled apparatus has a ROM for holding the MAC address of the controlled apparatus, and a network control IC that reads out the MAC address from the ROM and transmits it through a LAN to a control apparatus. The control apparatus receives the one or plurality of MAC addresses from the one or plurality of controlled apparatus through the LAN, stores the received one or plurality of MAC addresses in a cache memory and controls the one or plurality of controlled apparatus by using the one or plurality of MAC addresses stored in the cache memory.
    Type: Application
    Filed: May 17, 2004
    Publication date: June 9, 2005
    Inventors: Toshihiro Yamagishi, Hirofumi Yamashita
  • Publication number: 20050077830
    Abstract: A low-pressure discharge lamp (1) is provided that includes a glass tube (2) having an inner diameter in a range of 1 to 5 mm and a pair of electrodes (3) disposed at end portions in the glass tube (2). The pair of electrodes (3) contain at least one transition metal selected from transition metals of Groups IV to VI. Mercury and a rare gas containing argon and neon are sealed in an inner portion of the glass tube (2). A relationship between a cathode glow discharge density J and a composition index ? of the sealed rare gas of the low-pressure discharge lamp (1) satisfies the following expression ??J=I/(S·P2)?1.5? (where S represents an effective discharge surface area (mm2) of an electrode, I represents a RMS lamp current (mA), P represents a pressure (kPa) of a sealed rare gas, and ? represents a composition index of a sealed rare gas that is a constant expressed by ?=(90.5A+3.4N)×10?3 when a total of a composition ratio A of argon and a composition ratio N of neon is expressed by A+N=1).
    Type: Application
    Filed: July 17, 2003
    Publication date: April 14, 2005
    Inventors: Hirofumi Yamashita, Haruo Yamazaki, Toshihiro Terada, Shinji Kihara
  • Patent number: 6853139
    Abstract: The present invention has an object to provide a cold-cathode discharge lamp which can suppress sputtering on a lead-in wire and reduce consumption of mercury so as to achieve a longer lifetime without increasing an amount of applied mercury. The cold-cathode discharge lamp of the present invention is characterized in that a lead-in wire connected to a cylindrical electrode in a lighting tube is made of a material same as a material that forms the cylindrical electrode. It is possible to suppress concentration negative glow discharge shifted to the lead-in wire and to allow the electrode to be covered with even negative glow discharge. Thus, it is possible to reduce mercury consumed by excessive sputtering on the outer surface of the internal lead-in wire and to achieve a longer lifetime of the cold-cathode discharge lamp.
    Type: Grant
    Filed: March 27, 2002
    Date of Patent: February 8, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hirofumi Yamashita, Haruo Yamazaki, Toshihiro Terada, Shinji Kihara
  • Publication number: 20050012839
    Abstract: An MOS-type solid-state imaging apparatus includes an imaging region formed by two-dimensionally arranging unit cells serving as photoelectric conversion portions on a semiconductor substrate, a plurality of vertical address lines arranged in a row direction of the imaging region to select a row of unit cells to be addressed, a plurality of vertical signal lines arranged in a column direction of the imaging region to read out signals from the unit cells in each column, a plurality of load transistors each connected to one end of each of the vertical signal lines, and a plurality of horizontal selection transistors each connected to the other end of each of the vertical signal lines.
    Type: Application
    Filed: August 12, 2004
    Publication date: January 20, 2005
    Inventors: Yoshiyuki Matsunaga, Shinji Ohsawa, Nobuo Nakamura, Hirofumi Yamashita, Hiroki Miura
  • Patent number: 6800997
    Abstract: The present invention has an object to provide a cold-cathode fluorescent lamp which can suppress sputtering caused by electric discharge and reduce consumption of mercury so as to achieve a longer lifetime even if a lamp current is large and a lighting tube has a small diameter. The cold-cathode fluorescent lamp according to the present invention is characterized in that a distance between the inner surface of the lighting tube and the outer surface of a cylindrical electrode is set such that electric discharge develops mainly on the inner surface of the cylindrical electrode. When the lighting tube has an inside diameter D1 of 1 to 6 mm and the maximum lamp current is 5 mA or more, an outside diameter D2 of the cylinder electrode is preferably set at D1−0.4 [mm]≦D2<D1.
    Type: Grant
    Filed: March 27, 2002
    Date of Patent: October 5, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hirofumi Yamashita, Haruo Yamazaki, Toshihiro Terada, Shinji Kihara
  • Publication number: 20040189204
    Abstract: The present invention has an object to provide a cold-cathode fluorescent lamp which can suppress sputtering caused by electric discharge and reduce consumption of mercury so as to achieve a longer lifetime even if a lamp current is large and a lighting tube has a small diameter. The cold-cathode fluorescent lamp according to the present invention is characterized in that a distance between the inner surface of the lighting tube and the outer surface of a cylindrical electrode is set such that electric discharge develops mainly on the inner surface of the cylindrical electrode. When the lighting tube has an inside diameter D1 of 1 to 6 mm and the maximum lamp current is 5 mA or more, an outside diameter D2 of the cylinder electrode is preferably set at D1−0.4 [mm]≦D2<D1.
    Type: Application
    Filed: April 6, 2004
    Publication date: September 30, 2004
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hirofumi Yamashita, Haruo Yamazaki, Toshihiro Terada, Shinji Kihara
  • Patent number: 6795121
    Abstract: An MOS-type solid-state imaging apparatus includes an imaging region formed by two-dimensionally arranging unit cells serving as photoelectric conversion portions on a semiconductor substrate, a plurality of vertical address lines arranged in a row direction of the imaging region to select a row of unit cells to be addressed, a plurality of vertical signal lines arranged in a column direction of the imaging region to read out signals from the unit cells in each column, a plurality of load transistors each connected to one end of each of the vertical signal lines, and a plurality of horizontal selection transistors each connected to the other end of each of the vertical signal lines.
    Type: Grant
    Filed: December 12, 2000
    Date of Patent: September 21, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshiyuki Matsunaga, Shinji Ohsawa, Nobuo Nakamura, Hirofumi Yamashita, Hiroki Miura
  • Publication number: 20040132262
    Abstract: A solid-state imaging device comprises: unit cells in matrix where rows and columns of them are arranged in an upper surface of a semiconductor substrate, each of the unit cells including a photodiode that develops a certain level of signal charge in response to an amount of incident light and accumulates the signal charge, and a readout circuit for reading the signal charge from the photodiode, interlayer films laid over the semiconductor substrate and having wiring layers provided therein, light shield film formed over the interlayer films and having an aperture provided right above the photodiode in each of the unit cells, trains of first light shield upright barrier walls located in a space between two adjacent unit cells arranged in the same column, and trains of second light shield upright barrier walls located in a space between the adjacent unit cells in the same row, the first and second light shield upright barrier walls being embedded in the interlayer films between the semiconductor substrate and
    Type: Application
    Filed: September 4, 2003
    Publication date: July 8, 2004
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Ayabe, Hirofumi Yamashita, Ikuko Inoue, Yuichiro Egi
  • Publication number: 20040108502
    Abstract: The present invention provides a solid-state image pickup apparatus which is able to easily discharge signal charges in a signal accumulating section and which is free from reduction in the dynamic range of the element, thermal noise in a dark state, an image-lag and so forth even if the pixel size of the MOS solid-state image pickup apparatus is reduced, the voltage of a reading gate is lowered and the concentration in the well is raised. The solid-state image pickup apparatus according to the present invention incorporates a p-type silicon substrate having a surface on which a p+ diffusion layer for constituting a photoelectric conversion region and a drain of a reading MOS field effect transistor are formed. A signal accumulating section formed by an n-type diffusion layer is formed below the p+ diffusion layer. A gate electrode of the MOS field effect transistor is, on the surface of the substrate, formed between the p+ diffusion layer and the drain.
    Type: Application
    Filed: December 5, 2003
    Publication date: June 10, 2004
    Inventors: Nobuo Nakamura, Hisanori Ihara, Ikuko Inoue, Hidenori Shibata, Akiko Nomachi, Yoshiyuki Shioyama, Hidetoshi Nozaki, Masako Hori, Akira Makabe, Hiroshi Naruse, Hideki Inokuma, Seigo Abe, Hirofumi Yamashita, Tetsuya Yamaguchi
  • Patent number: 6690423
    Abstract: The present invention provides a solid-state image pickup apparatus which is able to easily discharge signal charges in a signal accumulating section and which is free from reduction in the dynamic range of the element, thermal noise in a dark state, an image-lag and so forth even if the pixel size of the MOS solid-state image pickup apparatus is reduced, the voltage of a reading gate is lowered and the concentration in the well is raised. The solid-state image pickup apparatus according to the present invention incorporates a p-type silicon substrate having a surface on which a p+ diffusion layer for constituting a photoelectric conversion region and a drain of a reading MOS field effect transistor are formed. A signal accumulating section formed by an n-type diffusion layer is formed below the p+ diffusion layer. A gate electrode of the MOS field effect transistor is, on the surface of the substrate, formed between the p+ diffusion layer and the drain.
    Type: Grant
    Filed: March 19, 1999
    Date of Patent: February 10, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Nobuo Nakamura, Hisanori Ihara, Ikuko Inoue, Hidenori Shibata, Akiko Nomachi, Yoshiyuki Shioyama, Hidetoshi Nozaki, Masako Hori, Akira Makabe, Hiroshi Naruse, Hideki Inokuma, Seigo Abe, Hirofumi Yamashita, Tetsuya Yamaguchi
  • Patent number: 6674470
    Abstract: A solid state imaging device comprises a plurality of unit cells formed in a surface region of a semiconductor substrate. Each of the unit cells comprises a photoelectric converter, an MOS-type read-out transistor for reading a signal from the photoelectric converter, an MOS-type amplifying transistor having a gate connected to a drain of the read-out transistor and for amplifying the signal read by the read-out transistor, a reset transistor having a source connected to the drain of the read-out transistor and for resetting a potential of a gate of the amplifying transistor, and an addressing element connected in series to the amplifying transistor and for selecting the unit cell. The read-out transistor is formed in a first device region in the semiconductor substrate. The reset transistor is formed in a second device region in the semiconductor substrate.
    Type: Grant
    Filed: September 19, 1997
    Date of Patent: January 6, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Nagataka Tanaka, Eiji Oba, Keiji Mabuchi, Michio Sasaki, Ryohei Miyagawa, Hirofumi Yamashita, Yoshinori Iida, Hisanori Ihara, Tetsuya Yamaguchi
  • Patent number: 6642087
    Abstract: A readout gate electrode is selectively formed on a silicon substrate. An N-type drain region is formed at one end of the readout gate electrode, and an N-type signal storage region is formed at the other end thereof. A P+-type surface shield region is selectively epitaxial-grown on the signal storage region, and a silicide block layer is formed on the surface shield region to cover at least part of the signal storage region. A Ti silicide film is selective epitaxial-grown on the drain region.
    Type: Grant
    Filed: January 10, 2003
    Date of Patent: November 4, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hidetoshi Nozaki, Ikuko Inoue, Hirofumi Yamashita
  • Publication number: 20030137008
    Abstract: A readout gate electrode is selectively formed on a silicon substrate. An N-type drain region is formed at one end of the readout gate electrode, and an N-type signal storage region is formed at the other end thereof. A P+-type surface shield region is selectively epitaxial-grown on the signal storage region, and a silicide block layer is formed on the surface shield region to cover at least part of the signal storage region. A Ti silicide film is selective epitaxial-grown on the drain region.
    Type: Application
    Filed: January 10, 2003
    Publication date: July 24, 2003
    Inventors: Hidetoshi Nozaki, Ikuko Inoue, Hirofumi Yamashita
  • Publication number: 20030127667
    Abstract: The invention is regarding to solid-state imaging device.
    Type: Application
    Filed: November 5, 2002
    Publication date: July 10, 2003
    Inventors: Ikuko Inoue, Hirofumi Yamashita, Hidetoshi Nozaki
  • Patent number: 6570222
    Abstract: A readout gate electrode is selectively formed on a silicon substrate. An N-type drain region is formed at one end of the readout gate electrode, and an N-type signal storage region is formed at the other end thereof. A P+-type surface shield region is selectively epitaxial-grown on the signal storage region, and a silicide block layer is formed on the surface shield region to cover at least part of the signal storage region. A Ti silicide film is selective epitaxial-grown on the drain region.
    Type: Grant
    Filed: March 9, 2001
    Date of Patent: May 27, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hidetoshi Nozaki, Ikuko Inoue, Hirofumi Yamashita
  • Patent number: 6528342
    Abstract: This invention prevents an end portion of the LOCOS region having a large number of defects of an MOS sensor from depletion and thereby reduces the leak current that occurs in the defects in the end portion of the LOCOS region. An n-type layer region is formed in a surface area of a p-type substrate for constituting a photodiode with the p-type layer. A LOCOS region is formed on a p+-type layer in a surface area of the silicon substrate as device separation region by oxidizing part of the silicon substrate. The n-type layer region and the LOCOS region are separated from each other by a predetermined distance. A contact region is formed and separated from the n-type layer region by a distance equal to the size of the gate electrode of the read-out transistor of the MOS sensor. A wiring layer is connected to the contact region. Then, a planarizing layer is formed to cover the n-type layer region, the LOCOS region, the gate electrode and the wiring layer.
    Type: Grant
    Filed: June 21, 2001
    Date of Patent: March 4, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ryohei Miyagawa, Hirofumi Yamashita, Michio Sasaki, Eiji Oba, Nagataka Tanaka, Keiji Mabuchi
  • Publication number: 20030039598
    Abstract: An exhaust gas purifying filter that does not break and melt and has high capacity to remove particulate matter, and a method of manufacturing the same, are provided.
    Type: Application
    Filed: March 22, 2002
    Publication date: February 27, 2003
    Applicant: DENSO CORPORATION
    Inventors: Mamoru Nishimura, Mikio Ishihara, Hirofumi Yamashita, Hiromi Sano
  • Publication number: 20020195544
    Abstract: An image input section and a signal processing section are provided. The image input section includes an array of pixel in which a plurality of pixels having a CMOS type photoelectric converting element for converting incident light to an electric signal are arranged in a matrix, and a data read-out circuit having the same number of A/D converters as the number of the pixels arranged in one row of the array of pixel and serving to convert the analog signal converted by the pixels into a digital signal and to output the digital signal. The signal processing section includes plurality of processors. Each of the processors includes a plurality of processing elements (PE) provided on the A/D converter provided in the data read-out circuit by one to one. Moreover, a plurality of PEs provided in each of the processors have the same data processing function in the same processor. Furthermore, the PEs in the processor carry out a signal processing in parallel in response to an instruction.
    Type: Application
    Filed: July 16, 2002
    Publication date: December 26, 2002
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hirofumi Yamashita, Charles G. Sodini
  • Patent number: 6486498
    Abstract: A solid-state imaging device includes a semiconductor substrate including a surface region of a second conductivity type, and plural unit pixels arranged in a matrix form on the surface region of the second conductivity type. Each of the unit pixels includes a first semiconductor region of a first conductivity type separated by a preset distance from the surface of the surface region in the depth direction and accumulates signal charges obtained by photo-electrical conversion of input light, and a gate electrode formed above the surface region, adjacent to the first semiconductor region and controlling readout of the signal charge accumulated in the first semiconductor region, end portions of the gate electrode and the first semiconductor region separated by a preset distance in a horizontal direction. Thus, the signal charge can be easily read-out and occurrence of thermal noise at the dark time, dark current noise, image-lag can be suppressed.
    Type: Grant
    Filed: September 20, 2001
    Date of Patent: November 26, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hirofumi Yamashita