Abstract: A multiprocessor in which a plurality of processors are connected via a system bus. The multiprocessor includes processor groups each having at least one processor, a main storage memory, a cache memory, a cache control unit, a directory memory, and a directory control unit. The directory control unit includes an invalidation command issuing unit that issues a cache line invalidation command to all reference designations stored in the directory memory in cache lines. Thus the device process time can be shortened by reducing the frequency that cache invalidation commands are issued from the cache memory.

Abstract: A multiprocessor in which a plurality of processors are connected via a system bus. The multiprocessor includes processor groups each having at least one processor, a main storage memory, a cache memory, a cache control unit, a directory memory, and a directory control unit. The directory control unit includes an invalidation command issuing unit that issues a cache line invalidation command to all reference designations stored in the directory memory in cache lines. Thus the device process time can be shortened by reducing the frequency that cache invalidation commands are issued from the cache memory.

Abstract: A plurality of processors, each with caches provided for a plurality of processor modules and a local storage in which a main storage is distributed and arranged are mutually connected through an internal snoop bus. The processor modules are mutually connected through a second system bus. By using two separate buses, cache coherence operations within a processor group is kept separate from cache coherence operations outside the processor group.

Abstract: An asynchronous access system for a computer system includes processing modules performing processes, at least one shared system memory module, and a system bus connecting the processing modules and the shared system memory module. Each of the processing modules includes a processor, a plurality of buffers coupled to the processor and to the system bus, and a controlling unit for writing data from the plurality of processors into the shared system memory module. Data is written into the shared system memory module by a processor generating write instructions to write data via the plurality of buffers and the system bus. The controlling unit controls the writing such that one writing instruction writes data into a plurality of buffers, then transfers the data to the shared system memory module via the system bus, with another writing instruction writing additional data into another plurality of buffers and transferring the additional data to the shared system memory module.

Abstract: An asynchronous access system includes a system bus, at least one processing module provided with a main memory, a central processing unit and a first connection unit which connects to the system bus, and at least one shared memory module provided with a shared memory unit and a second connection unit which connects to the system bus. The first connection unit within the processing module makes a block read request to the shared memory module via the system bus when the first connection unit recognizes a read from the shared memory module requested from the central processing unit.

Abstract: In a multi-processor system in which a plurality of units such as a CPU serving as an information processing unit and an I/O control unit can be connected over a system bus, when the plurality of units issue use requests for the system bus, a bus arbiter grants a use authority for the system bus to a specific unit in consideration with priority orders. The bus arbiter is connected to the respective units over at least one specific signal line. The specific signal line conforms to a specific transmission rule in a normal control mode, whereby a specific signal is transmitted over the specific signal line. When a unit is not connected, at least one specific signal line in the bus arbiter is fixed to a state unfeasible in a normal control mode. The specific signal line is monitored if necessary. When the specific signal line linked with a unit is controlled under a specific transmission rule, the unit is recognized as connected.

Abstract: A message control system is for a data communication system which takes the form of a loosely coupled multiprocessing system in which a plurality of processing modules respectively having a memory unit are coupled to each other via a system bus. In this message control system, a memory unit (13) within each processing module (10) includes a data processing part (14) which is a software running on a central processing unit (11) within its own processing module, and a buffer (16, 17) which stores a transmitting message. A connection unit (13) within each processing module (10) at least includes a plurality of logical transmitting ports (21) for successively reading out the message which is expanded in the buffer (16, 17) and transmits the same as a continuous message, a plurality of logical receiving ports (22) for storing the message, a transmission system connecting means (23), and a reception system connecting means (24).

Abstract: In an asynchronous access system for a multiprocessor system having a plurality of processor modules connected to a system bus and at least one shared memory module connected to the system bus, each of the processor modules includes a processor and an internal buffer. The processor writes data into the internal buffer, and the data is read from the internal buffer and is written into the shared memory via the system bus. The asynchronous access system includes a first unit, provided in each of the processor modules, for detecting a predetermined situation regarding a data write from the processor to the shared memory, and a second unit, provided in each of the processor modules, for causing the data stored in the internal buffer to be written into the shared memory module when the first unit detects the predetermined situation.

Abstract: The present invention provides a cache-data transfer system improving a cache-hit rate by making a block size of the external cache memory longer than the block size of an internal cache memory. The system makes a block size of the external cache memory longer than a block size of the internal cache memory by inserting a data transfer process which transfers a data from the storage means to only the external cache memory during a data transfer process from the storage means to the internal cache memory and the external cache memory.

Abstract: An exclusive control system is provided in a system having a memory module and a plurality of processing modules sharing the memory module, each of the plurality of processing modules exclusively accessing the memory module while prohibiting other processing modules from accessing the memory module. The exclusive control system includes a determination unit for determining whether or not a process executed in response to an access request from a processor module among the plurality of processing modules is normally completed in the memory module, and a retry unit for, when the determination unit determines that the process executed in response to the access request is not normally completed, retrying the process while maintaining a state in which other processing modules are prohibited from accessing the memory module.

Abstract: A message control system for a data communication system in the form of a loosely coupled multiprocessing system, in which a plurality of processing modules having a memory unit are coupled to each other via a system bus. In this message control system, a memory unit, within each processing module, includes a data processing part which is in software running on a central processing unit within its own processing module, a descriptor which manages address and data length information of a storage region for a message in the form of a chain, and a buffer which decomposes and stores a transmitting message. A connection unit within each processing module includes logical transmitting ports and a logical receiving port.

Abstract: In a bus arbiter connected to a system bus of a multi-processor system having a plurality of modules respectively having processors, a first unit detects an abnormality in the multi-processor system on the basis of an internal state of the bus arbiter and a predetermined signal transferred via the system bus. A second unit initializes the internal state of the bus arbiter to restart the bus arbiter when the first unit detects an abnormality.

Abstract: A check system for checking a comparison check function of an information processing apparatus which includes first and second microprocessors includes a check part for supplying mutually different data to the first and second microprocessors when checking the comparison check function, and a comparing part for comparing data which are output from the first and second microprocessors in response to the mutually different data supplied to the first and second microprocessors. The comparing part generates an alarm when the data output from the first and second microprocessors are mutually different, so that correct operation of the comparison check function can be verified by the alarm when checking the comparison check function.

Abstract: When a unit connected to a data transfer bus on which data transfer is controlled synchronously with a bus cycle makes a request for using the bus, permission is granted to one of the units which have made the request. The permission to use the bus is switched over at a bus cycle when data transfer is completed in the unit. Consequently, the bus cycle can be shortened, and the speed of the data transfer by the bus can be increased. To achieve this, the unit which has granted permission to use the bus sends out a notifying signal notifying switch over of the permission to use the bus at a bus cycle, which precedes the bus cycle when data transfer is completed. The permission to use the bus granted to the unit, which has completed data transfer, is cancelled on the basis of the notifying signal at the bus cycle when data transfer is completed. Permission to use the bus is granted to a subsequent unit at that bus cycle when there is the subsequent unit which is requested use of the bus.