Patents by Inventor Hirohiko Yamamoto

Hirohiko Yamamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10975503
    Abstract: A skin material for vehicle interior is bonded to a resinous vehicle interior base. The skin material for vehicle interior includes a woven fabric woven by using synthetic resin fibers, side emission type optical fibers, and heat fusible fibers as warps or wefts. The synthetic resin fibers and the side emission type optical fibers adjacent to the synthetic resin fibers are bonded in respective longitudinal directions thereof by the heat fusible fibers. Even when a plurality of the side emission type optical fibers are woven between the adjacent synthetic resin fibers, the adjacent side emission type optical fibers may be bonded to each other in the longitudinal direction by the heat fusible fibers. The heat fusible fibers may be obtained by twisting multifilaments and heat fusion yarns having a melting point lower than that of the multifilaments, and the multifilaments remain as constituent yarns after the bonding.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: April 13, 2021
    Assignees: TOYOTA BOSHOKU KABUSHIKI KAISHA, DAIKI CO., LTD.
    Inventors: Takamasa Yamada, Hirohiko Sakai, Takayoshi Yamamoto
  • Patent number: 10906460
    Abstract: There is provided a skin material for vehicle interior, which is woven from a side emission type optical fiber and a synthetic resin fiber, forms a design surface in a vehicle compartment and functions as an illumination. The skin material for vehicle interior is a skin material 10 for vehicle interior including a woven fabric woven by using a synthetic resin fiber and a side emission type optical fiber as warp or weft, wherein the ratio (dS/df) of the fineness (dS) of the synthetic resin fiber to the fineness (df) of the side emission type optical fiber ranges from 1.5 to 7.0. When the synthetic resin fiber is a multifilament 11, the ratio (dS1/df) of the fineness (dS1) thereof to the fineness (df) of the side emission type optical fiber 3 ranges from 2.0 to 7.0. Also, when the synthetic resin fiber is a monofilament, the ratio (dS2/df) of the fineness (dS2) thereof to the fineness (df) of the side emission type optical fiber ranges from 1.5 to 6.0.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: February 2, 2021
    Assignees: TOYOTA BOSHOKU KABUSHIKI KAISHA, DAIKI CO., LTD.
    Inventors: Takamasa Yamada, Atsuhiko Ito, Takayoshi Yamamoto, Hirohiko Sakai, Kousei Egawa
  • Patent number: 10328850
    Abstract: Provided is a skin material which forms a vehicle interior design surface, functions as lighting, and suppresses the fray of side emission type optical fibers. The skin material includes a woven fabric woven by using synthetic resin fibers, side emission type optical fibers, and heat fusible fibers as warps or wefts. A ratio (dS/df) of fineness (dS) of the synthetic resin fibers to fineness (df) of the side emission type optical fibers is from 1.5 to 7.0. The synthetic resin fibers and the side emission type optical fibers adjacent to the synthetic resin fibers are bonded in respective longitudinal directions thereof by the heat fusible fibers. When a plurality of the side emission type optical fibers are woven between the adjacent synthetic resin fibers, the adjacent side emission type optical fibers are bonded to each other in the longitudinal direction by the heat fusible fibers.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: June 25, 2019
    Assignees: TOYOTA BOSHOKU KABUSHIKI KAISHA, DAIKI CO., LTD.
    Inventors: Takamasa Yamada, Hirohiko Sakai, Takayoshi Yamamoto
  • Patent number: 9337147
    Abstract: A semiconductor device includes grooves defining an active region, including a MISFET, and dummy regions. A first interlayer insulation film is formed over the MISFET, the active region and the dummy regions. A first wiring, and first and second dummy wirings are formed over the first interlayer insulation film. A second interlayer insulation film is formed over the first wiring and the dummy wirings. The second dummy wirings are arranged between the first wiring and the first dummy wirings, and the pitch of the first dummy wirings is larger than that of the second dummy wirings. In planar view, the first and second dummy wirings are arranged over the dummy regions, and the size of each of the first dummy wirings is larger than size of each of the second dummy wirings. The first wiring and the first and second dummy wirings are formed of copper as a major component.
    Type: Grant
    Filed: June 19, 2015
    Date of Patent: May 10, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Kenichi Kuroda, Kozo Watanabe, Hirohiko Yamamoto
  • Publication number: 20150287679
    Abstract: A semiconductor device includes grooves defining an active region, including a MISFET, and dummy regions. A first interlayer insulation film is formed over the MISFET, the active region and the dummy regions. A first wiring, and first and second dummy wirings are formed over the first interlayer insulation film. A second interlayer insulation film is formed over the first wiring and the dummy wirings. The second dummy wirings are arranged between the first wiring and the first dummy wirings, and the pitch of the first dummy wirings is larger than that of the second dummy wirings. In planar view, the first and second dummy wirings are arranged over the dummy regions, and the size of each of the first dummy wirings is larger than size of each of the second dummy wirings. The first wiring and the first and second dummy wirings are formed of copper as a major component.
    Type: Application
    Filed: June 19, 2015
    Publication date: October 8, 2015
    Inventors: Kenichi KURODA, Kozo WATANABE, Hirohiko YAMAMOTO
  • Patent number: 9064926
    Abstract: There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP1 of relatively wider area and the second dummy pattern DP2 of relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DP1 occupy a relatively wide region among the dummy region FA.
    Type: Grant
    Filed: December 9, 2013
    Date of Patent: June 23, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Kenichi Kuroda, Kozo Watanabe, Hirohiko Yamamoto
  • Publication number: 20140099770
    Abstract: There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP1 of relatively wider area and the second dummy pattern DP2 of relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DP1 occupy a relatively wide region among the dummy region FA.
    Type: Application
    Filed: December 9, 2013
    Publication date: April 10, 2014
    Applicants: Hitachi ULSI Systems Co., Ltd., Renesas Electronics Corporation
    Inventors: Kenichi Kuroda, Kozo Watanabe, Hirohiko Yamamoto
  • Patent number: 8604505
    Abstract: There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP1 of relatively wider area and the second dummy pattern DP2 of relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DP1 occupy a relatively wide region among the dummy region FA.
    Type: Grant
    Filed: April 8, 2013
    Date of Patent: December 10, 2013
    Assignees: Renesas Electronics Corporation, Hitachi ULSI Systems Co., Ltd.
    Inventors: Kenichi Kuroda, Kozo Watanabe, Hirohiko Yamamoto
  • Publication number: 20130241029
    Abstract: There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP1 of relatively wider area and the second dummy pattern DP2 of relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DP1 occupy a relatively wide region among the dummy region FA.
    Type: Application
    Filed: April 8, 2013
    Publication date: September 19, 2013
    Applicants: HITACHI ULSI SYSTEMS CO., LTD., RENESAS ELECTRONICS CORPORATION
    Inventors: Kenichi KURODA, Kozo WATANABE, Hirohiko YAMAMOTO
  • Patent number: 8426969
    Abstract: There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP1 of relatively wider area and the second dummy pattern DP2 of relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DP1 occupy a relatively wide region among the dummy region FA.
    Type: Grant
    Filed: January 31, 2012
    Date of Patent: April 23, 2013
    Assignees: Renesas Electronics Corporation, Hitachi ULSI Systems Co., Ltd.
    Inventors: Kenichi Kuroda, Kozo Watanabe, Hirohiko Yamamoto
  • Patent number: 8334481
    Abstract: A mounting table body made of ceramic includes power-receiving conductor portions and buried therein. A surface of mounting table body is formed with a recessed connection hole and a connection terminal electrically jointed to the power-receiving conductor portion and exposed into the connection hole, the connection terminal being made of a high-melting-point metal, an alloy thereof or a compound thereof. A power-feeding line member provided with a power-feeding connector portion is inserted at its leading end portion into the connection hole to feed electricity to the power-receiving conductor portion. A stress relaxing member is interposed between the connection terminal and the power-feeding connector portion. The stress relaxing member and the connection terminal are jointed together by a brazing material. The stress relaxing member is made of a metal free from cobalt and nickel or an alloy thereof.
    Type: Grant
    Filed: July 17, 2009
    Date of Patent: December 18, 2012
    Assignee: Tokyo Electron Limited
    Inventors: Tomohito Komatsu, Hirohiko Yamamoto, Daisuke Toriya
  • Publication number: 20120126360
    Abstract: There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP1 of relatively wider area and the second dummy pattern DP2 of relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DP1 occupy a relatively wide region among the dummy region FA.
    Type: Application
    Filed: January 31, 2012
    Publication date: May 24, 2012
    Inventors: Kenichi KURODA, Kozo Watanabe, Hirohiko Yamamoto
  • Patent number: 8119495
    Abstract: There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP1 of relatively wider area and the second dummy pattern DP2 of relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DP1 occupy a relatively wide region among the dummy region FA.
    Type: Grant
    Filed: April 28, 2011
    Date of Patent: February 21, 2012
    Assignees: Renesas Electronics Corporation, Hitachi ULSI Systems Co., Ltd.
    Inventors: Kenichi Kuroda, Kozo Watanabe, Hirohiko Yamamoto
  • Publication number: 20110207288
    Abstract: There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP1 of relatively wider area and the second dummy pattern DP2 of relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DP1 occupy a relatively wide region among the dummy region FA.
    Type: Application
    Filed: April 28, 2011
    Publication date: August 25, 2011
    Inventors: Kenichi KURODA, Kozo Watanabe, Hirohiko Yamamoto
  • Patent number: 7948086
    Abstract: There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP1 of relatively wider area and the second dummy pattern DP2 of relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DP1 occupy a relatively wide region among the dummy region FA.
    Type: Grant
    Filed: March 1, 2010
    Date of Patent: May 24, 2011
    Assignees: Renesas Electronics Corporation, Hitachi ULSI Systems Co., Ltd.
    Inventors: Kenichi Kuroda, Kozo Watanabe, Hirohiko Yamamoto
  • Publication number: 20100323313
    Abstract: There is provided a stage structure which can prevent the formation of a cool spot in the central portion of a stage, thereby preventing breakage of the stage, and can enhance the in-plane uniformity of heat treatment of a processing object. The stage structure, provided in a treatment container of a heat treatment apparatus, for placing thereon a semiconductor wafer W as a processing object to be heat treated, includes: a stage 52 for placing the processing object on it; and a cylindrical support post 54 jointed to the center of the lower surface of the stage and supporting the stage. A heat reflecting section 56 is provided at an upper position within the support post and close to the lower surface of the stage. The use of the heat reflecting section 56 prevents the formation of a cool spot in the central portion of the stage 54.
    Type: Application
    Filed: March 13, 2009
    Publication date: December 23, 2010
    Applicant: TOKYO ELECRON LIMITED
    Inventors: Daisuke Toriya, Hirohiko Yamamoto
  • Publication number: 20100155857
    Abstract: There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP1 of relatively wider area and the second dummy pattern DP2 of relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DP1 occupy a relatively wide region among the dummy region FA.
    Type: Application
    Filed: March 1, 2010
    Publication date: June 24, 2010
    Inventors: Kenichi KURODA, Kozo Watanabe, Hirohiko Yamamoto
  • Patent number: 7687914
    Abstract: There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP1 of relatively wider area and the second dummy pattern DP2 of relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DP1 occupy a relatively wide region among the dummy region FA.
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: March 30, 2010
    Assignees: Renesas Technology Corporation, Hitachi ULSI Systems Co., Ltd.
    Inventors: Kenichi Kuroda, Kozo Watanabe, Hirohiko Yamamoto
  • Publication number: 20090277895
    Abstract: A mounting table body made of ceramic includes power-receiving conductor portions and buried therein. A surface of mounting table body is formed with a recessed connection hole and a connection terminal electrically jointed to the power-receiving conductor portion and exposed into the connection hole, the connection terminal being made of a high-melting-point metal, an alloy thereof or a compound thereof. A power-feeding line member provided with a power-feeding connector portion is inserted at its leading end portion into the connection hole to feed electricity to the power-receiving conductor portion. A stress relaxing member is interposed between the connection terminal and the power-feeding connector portion. The stress relaxing member and the connection terminal are jointed together by a brazing material. The stress relaxing member is made of a metal free from cobalt and nickel or an alloy thereof.
    Type: Application
    Filed: July 17, 2009
    Publication date: November 12, 2009
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Tomohito KOMATSU, Hirohiko Yamamoto, Daisuke Toriya
  • Patent number: 7589423
    Abstract: There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP1 of relatively wider area and the second dummy pattern DP2 of relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DP1 occupy a relatively wide region among the dummy region FA.
    Type: Grant
    Filed: May 24, 2007
    Date of Patent: September 15, 2009
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.
    Inventors: Kenichi Kuroda, Kozo Watanabe, Hirohiko Yamamoto