Patents by Inventor Hirohisa Yamaguchi

Hirohisa Yamaguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6801588
    Abstract: A combined channel and entropy decoder is provided that achieves a significant bit-error rate improvement using likelihood values (61) instead of conventional bits. The likelihood values are stored in a buffer (62). A unique code-word is searched in the bit pattern or in the likelihood value. When a unique code-word is found at the identifier (63), candidate code-words are loaded into computation units where each unit computes code-word likelihood for a given code-word bit pattern. The code-word likelihood values are compared and the selected code information is fed back to the code-word controller 67 to proceed to the next-step decoding.
    Type: Grant
    Filed: September 22, 2000
    Date of Patent: October 5, 2004
    Assignee: Texas Instruments Incorporated
    Inventor: Hirohisa Yamaguchi
  • Publication number: 20040179580
    Abstract: The ultra wide band communication system of the present invention includes a transmitter (station) and a receiver (station). The transmitter and the receiver employ spreading code comprised of code groups, which respectively comprise varied, auto-correlated codes. Consecutive information bits are spread and de-spread with differing code and the code groups are correlated with each other (e.g., orthogonal) so as to reduce channel impulse response estimation noise. At the receiver, subsequent channel estimates can be added or averaged with an initial channel estimate so as to reduce the channel impulse response estimation noise and thereby provide a relatively more accurate channel response.
    Type: Application
    Filed: March 24, 2003
    Publication date: September 16, 2004
    Inventor: Hirohisa Yamaguchi
  • Publication number: 20040156421
    Abstract: The ultra wide band communication system of the present invention includes a transmitter (station) and a receiver (station). The transmitter employs correlated spreading code such that consecutive information bits are spread with differing code. The receiver includes an analog circuit filter comprised of a cascade of unit components that appropriately de-spread and accumulate a received signal to obtain a transmitted signal without substantial hardware complexity. The unit components are substantially comprised of analog components including, a sample and hold circuit, a leaky integrator, and a multiplier.
    Type: Application
    Filed: February 10, 2003
    Publication date: August 12, 2004
    Inventor: Hirohisa Yamaguchi
  • Patent number: 6697492
    Abstract: A technique for realizing high-speed and high-precision acoustic reproduction using acoustic speakers. The audio signal processing system has a sub-band analysis filter bank that divides the entire frequency band of an input audio signal into multiple sub-bands. Filter coefficient calculation circuits identify equalizable sub-bands and compares equalizable sub-bands and corresponding sub-bands from output audio signals in order to calculate filter coefficients. A sub-band convolution filter bank and a filter circuit perform frequency convolution on calculated filter coefficients for equalizable sub-bands and process input audio signals on the basis of this convolution.
    Type: Grant
    Filed: April 27, 1999
    Date of Patent: February 24, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Hirohisa Yamaguchi, Yoshito Higa
  • Patent number: 6687376
    Abstract: A circuit is designed with a first register circuit (364) arranged to store a state matrix. A memory circuit (710) is arranged to store a plurality of addressable matrices. A control circuit (700) is coupled to receive a delay value and a clock signal. The control circuit is arranged to address a selected matrix from the plurality of addressable matrices in response to the delay value and the clock signal. A backward register circuit (420) is coupled (712) to receive the selected matrix. The backward register circuit is arranged to produce a plurality of shifted matrices from the selected matrix in response to the clock signal. A logic circuit (330-354) is coupled to receive the state matrix, the selected matrix and the plurality of shifted matrices. The logic circuit produces a logical combination of the state matrix and each of the selected matrix and the plurality of shifted matrices.
    Type: Grant
    Filed: December 29, 1998
    Date of Patent: February 3, 2004
    Assignee: Texas Instruments Incorporated
    Inventor: Hirohisa Yamaguchi
  • Publication number: 20030227866
    Abstract: A multi-path equalization system for orthogonal frequency division multiplexing communication (OFDM) system includes a first estimator for estimating the channel characteristic using pilot signal. A divider is coupled to the estimator for dividing each sub-carrier with the channel characteristic to get the equalization to the data signal. A de-mapper uses the phase and amplitude correction of the channel estimate to recover the data signals. An improved channel estimation is provided by a repeat channel estimation feedback loop that includes the de-mapper a multiplier, an inverse fast Fourier transform (IFFT), a low pass filter and a fast Fourier transform (FFT). The improved channel estimation is obtained by multiplying at the multiplier the conjugate of the de-mapped data to the input sub-carriers and applying inverse FFT, low pass filtering and FFT to get the new channel estimate. Each sub-carrier is divided with new channel characteristic to get new equalization to the data signal.
    Type: Application
    Filed: June 6, 2002
    Publication date: December 11, 2003
    Inventor: Hirohisa Yamaguchi
  • Publication number: 20030119444
    Abstract: Cell search synchronization in spread spectrum communications systems using primary and second synchronization codes with symbol partitioning for shorter coherent combinations (despreading) which are combined non-coherently, and Fourier transform analysis automatically adjusts for phase rotation of the despread sub-symbols.
    Type: Application
    Filed: October 30, 2002
    Publication date: June 26, 2003
    Inventor: Hirohisa Yamaguchi
  • Patent number: 6480503
    Abstract: A circuit is designed with an encoder circuit (602) coupled to receive a data sequence. The encoder circuit produces a first encoded data sequence and a second encoded data sequence from the data sequence. A first spreading circuit (606) is coupled to receive the data sequence and the first encoded data sequence. The first spreading circuit produces a first modulated data sequence in response to a first code. A second spreading circuit (614) is coupled to receive the data sequence and the second encoded data sequence. The second spreading circuit produces a second modulated data sequence in response to a second code.
    Type: Grant
    Filed: March 1, 1999
    Date of Patent: November 12, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Hirohisa Yamaguchi, Mitsuhiko Yagyu
  • Publication number: 20020046011
    Abstract: A single-input double-output blind model system identification method for estimating a channel order and reducing communications errors in a transmitted data sequence s(n), wherein the channel is represented by h1 and h2. The method is performed according to a SIDO model.
    Type: Application
    Filed: August 7, 2001
    Publication date: April 18, 2002
    Inventors: Yoshito Higa, Shigenori Kinjo, Hirohisa Yamaguchi
  • Publication number: 20020003573
    Abstract: An image processing device has an image composition component that combines a plurality of image signals to obtain a single composite image signal, and an image compression coding component that compresses and encodes the single composite image signal so as to obtain a compression coded image signal.
    Type: Application
    Filed: June 19, 2001
    Publication date: January 10, 2002
    Applicant: TEAC CORPORATION
    Inventors: Hirohisa Yamaguchi, Masanori Wakamiya
  • Patent number: 6272661
    Abstract: A Viterbi decoder is disclosed that utilizes minimum memory for the decoding operation. A plurality of FIFOs are provided which are divided into two blocks of FIFOS, one for upper states and one for lower states. The operations are calculated utilizing previously stored branch metrics and then determining the new branch metric by retrieving information from the FIFOs, adding the new branch metric defined with the soft decision table and then selecting the most likely path therefrom, and discarding the other. This new branch metric is then stored back into the FIFOs to replace the old. Each branch metric calculation results in a determination of the most likely path for that state and also the decoded data bit for a given state associated with a received symbol. This is stored in a separate memory for each of the nodes, and thereafter, the output is decoded to retrieve the decoded bit stream.
    Type: Grant
    Filed: December 29, 1998
    Date of Patent: August 7, 2001
    Assignee: Texas Instruments Incorporated
    Inventor: Hirohisa Yamaguchi
  • Patent number: 6249551
    Abstract: An MPEG video playback method and system that reduces delay at the time of video reproduction of an MPEG-compressed video signal. The invention discloses a video reproduction method in a video reproduction system containing an error-correction means, an MPEG decoding means, and buffers. In one embodiment, the signal held in the buffer is output as the video playback signal (block 6), and the output from the MPEG decoding means is output as a video playback signal (block 5). An embodiment of a method and system in which the buffer is arranged upstream to the MPEG decoding means is also disclosed.
    Type: Grant
    Filed: December 19, 1996
    Date of Patent: June 19, 2001
    Assignee: Texas Instruments Incorporated
    Inventor: Hirohisa Yamaguchi
  • Patent number: 6236763
    Abstract: A method of and circuitry for removing noise artifacts in decompressed video signals. A group of pixels is selected from a larger matrix of pixels from adjacent rows and columns of the matrix. A plurality of different subgroups of the group of pixels is selected, each subgroup including the same centrally located pixel. The maximum energy intensity difference emanating from each pixel in each of the subgroups is measured and the maximum difference among the pixels in each subgroup is determined. The subgroup having the lowest maximum difference is selected and the weighed mean of the selected pixels in the subgroup is computed with weights chosen to provide more significance to pixels which are located closer to the centrally located pixel. The centrally located pixel is then filtered with a linear filter, the coefficients of which are determined by the sum of absolute differences between the weighed mean and the pixels in the subgroup.
    Type: Grant
    Filed: September 15, 1998
    Date of Patent: May 22, 2001
    Assignee: Texas Instruments Incorporated
    Inventors: Yiwan Wong, Hirohisa Yamaguchi
  • Patent number: 6188714
    Abstract: A parallel M-sequence generator is disclosed which outputs an identical bit stream of a serial M-sequence generator of equal chip length. In a parallel N-bit implementation, the first N bits of the sequence are read at the output, the remaining bits are shifted, and the new N bits are generated, all in one clock cycle. The effect of obtaining N bits at the output is to multiply the present contents of the shift register by a companion matrix of the Nth order. Linear combining elements (e.g. XOR gates) are selectively positioned to combine the contents of various delay elements of the parallel structure and feedback the results to other delay elements in order to produce the identical output of the serial structure.
    Type: Grant
    Filed: December 29, 1998
    Date of Patent: February 13, 2001
    Assignee: Texas Instruments Incorporated
    Inventor: Hirohisa Yamaguchi
  • Patent number: 5878173
    Abstract: Method and device for enabling high-speed write/read operation of image information in units of blocks, so as to fully meet the demand on high-speed operation of MPEG, etc. Eight memory arrays MA1-MA8 are parallelly-connected in image memory unit 10; hence, in each memory array MAi, image can be written/read individually under control of write address generating circuit 12, memory array control logic 14, and read address generating circuit 16. The input/output terminals of memory arrays MA1-MA8 are connected to half-pel operation circuit 24 through eight data registers DREG1-DREG8 of input/output buffer 18, eight row selectors YSEL1-YSEL8 and column selector XSEL of selector circuit 20, and data bus 22.
    Type: Grant
    Filed: October 16, 1996
    Date of Patent: March 2, 1999
    Assignee: Texas Instruments Incorporated
    Inventors: Masashi Hashimoto, Hirohisa Yamaguchi
  • Patent number: 5838967
    Abstract: An addition unit adds information for managing a plurality of image-data files to directory information packets. A managing unit utilizes the added information for managing the plurality of image-data files. A retrieving unit retrieves, in accordance with an input retrieving information, a desired image-data file from among the plurality of image-data files recorded on a recording medium. An image-data input and output interfacing unit interfaces for input and output of image-data files. A recording-medium interfacing unit interfaces for information input and output by means of the recording medium. An output video-signal producing unit produces a video signal for output, the producing being effected by converting the retrieved image-data file into a corresponding analog video signal and using the analog video signal as the video signal for output.
    Type: Grant
    Filed: December 29, 1994
    Date of Patent: November 17, 1998
    Assignee: Teac Corporation
    Inventors: Tetsuhisa Okayama, Yoshiaki Aoyama, Hiroyuki Hoshino, Hirohisa Yamaguchi
  • Patent number: 5815602
    Abstract: The objective of this invention is to provide a data processor which can perform motion estimation of moving images at high speed and high accuracy. The data processor according to this invention is equipped with Hadamard transformer (110), first stage processor (120), second stage processor (130), and motion compensation circuit (140). The Hadamard transformer (110) receives image data (12) of the current frame and image data (34) of the reference frame, and Hadamard transforms this image data. First stage processor (120) block matches the target block with the Hadamard coefficient of the reference frame using multiple low-frequency coefficients selected from the Hadamard transformed data. Second stage processor (130) refers to the block matching position obtained in first stage processor (120), determines the search range in the picture data of the reference frame, and obtains the motion vector of the target block in said search range.
    Type: Grant
    Filed: September 5, 1995
    Date of Patent: September 29, 1998
    Assignee: Texas Instruments Incorporated
    Inventors: Hideaki Ueda, Hirohisa Yamaguchi
  • Patent number: 5786857
    Abstract: An image-processing system in which harmful noises of image compression are effectively removed. The image processing system includes a transformation device for receiving m pixels.times.n lines of image information from an input and converting the image information via discrete cosine transformation to data represented in the frequency domain. A quantizer unit forms quantized data based on the frequency domain data received from the transformation device. A reverse quantization unit provides reverse quantized frequency domain data from the quantized data received from the quantizer unit. A second transformation device is connected to the reverse quantization unit for transforming the reverse quantized frequency domain data via inverse discrete cosine transformation to image information. A filtering unit is connected to the second transformation device for filtering the image information from the second transformation device based on the non-zero coefficient parameter.
    Type: Grant
    Filed: May 28, 1997
    Date of Patent: July 28, 1998
    Assignee: Texas Instruments Incorporated
    Inventor: Hirohisa Yamaguchi
  • Patent number: 5765160
    Abstract: The disclosed invention is a computer-implemented method for registering triggers for processing at the end of each transaction occurring in a database. This method positions a class where a given object exists; and for each trigger in the class, a determination is made if the trigger is in a trigger list of an object link. If it is not, a determination is made if a given object is in an object link of a transaction. If it is not, then the given object is inserted into the object link of the transaction; and then the trigger is inserted in a list of the object link. These steps are repeated until all triggers in the class have been processed. A determination is next made if there is a superclass of the class. If yes, then a superclass, is positioned and the steps are repeated for each trigger in the superclass (i.e., polymorphic trigger). Finally, if no superclass of the class exist, then the method is exited.
    Type: Grant
    Filed: August 1, 1996
    Date of Patent: June 9, 1998
    Assignee: Unisys Corp.
    Inventor: Hirohisa Yamaguchi
  • Patent number: 5511155
    Abstract: A method and apparatus for forming a synthesized optical image with all of the desired objects in focus. A prescribed number of optical images of the same scene are provided by recording an optical image at a respective focal distance and changing the focal distance for each additional optical image as recorded. The optical images are subjected to wavelet transformation to form a multi-resolution representation. The coefficients of the various multi-resolution representations are compared at the same position to detect the maximum spectral amplitudes. Based on the detected maximum spectral amplitudes, another multi-resolution representation is obtained. Then, an inverse wavelet transformation is performed to obtain the synthesized optical image.
    Type: Grant
    Filed: January 27, 1994
    Date of Patent: April 23, 1996
    Assignee: Texas Instruments Incorporated
    Inventor: Hirohisa Yamaguchi