Patents by Inventor Hirohito Watanabe

Hirohito Watanabe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230107088
    Abstract: Provided are novel determination techniques and systems enabling an AI process in which decisions are made from the viewpoint of allowing an expert to make a decision, and capable of providing a valid answer, even with a small amount of learning data, by adjusting errors in both the answer of the expert and the answer of AI. A system is configured to cause an AI process to be performed on subject teacher data for AI learning in which events of objects identified by identifying codes are divided into classes, and data pertaining to an object for which class determination of an event is required, and to receive class determination data obtained by the AI process.
    Type: Application
    Filed: March 25, 2021
    Publication date: April 6, 2023
    Inventors: Yasuki KIHARA, Michiko MORIYAMA, Kana KAZAWA, Hirohito WATANABE, Takayuki NAKAMURA, Noriaki YOSHIKAI, Haruhiro NAGAHISA
  • Publication number: 20180306184
    Abstract: A vane pump includes a rotor; a plurality of vanes; a cam ring; a second side plate; a suction port provided in the second side plate, the suction port being configured to guide working fluid to the pump chambers; a pump cover arranged so as to sandwich the second side plate with the cam ring; and a low-pressure chamber formed in the pump cover, the low-pressure chamber having an opening portion communicating with the suction port. The suction port is arranged so as to be shifted towards a forward side of in a rotating direction of the rotor with respect to the opening portion of the low-pressure chamber.
    Type: Application
    Filed: September 16, 2016
    Publication date: October 25, 2018
    Applicant: KYB Corporation
    Inventors: Yoshinari NAKAMURA, Shinji YAKABE, Kazunari SUZUKI, Koichiro AKATSUKA, Hirohito WATANABE
  • Patent number: 9795027
    Abstract: To suppress occurrence of a difference in transmission time due to a difference in length between signal lines, there is provided a printed wiring board having: an insulating substrate (10); a first signal line (L31) formed on the insulating substrate (10); a second signal line (L32) having a shorter length than that of the first signal line (L31); and a ground layer (30) formed for the first signal line (L31) and the second signal line (L31) via an insulating material (10). The ground layer (30) includes a first ground layer (G31) corresponding to a first region (D1) and a second ground layer (G32) corresponding to a second region (D2). The first region (D1) is defined based on the first signal line (L31) and has a first predetermined width (W31). The second region (D2) is defined based on the second signal line (L32) and has a second predetermined width (W32). The first ground layer (G31) has a remaining ratio lower than a remaining ratio of the second ground layer (G32).
    Type: Grant
    Filed: May 20, 2015
    Date of Patent: October 17, 2017
    Assignee: FUJIKURA LTD.
    Inventors: Hirohito Watanabe, Taiji Ogawa
  • Patent number: 9549460
    Abstract: To suppress occurrence of a difference in transmission time due to a difference in length between signal lines, there is provided a printed wiring board having: an insulating substrate (10); a first signal line (L31A) that constitutes differential signal lines formed on the insulating substrate (10) and includes a curved portion; a second signal line (L31B) provided along the first signal line (L31A) and side by side inside the curved portion; and a ground layer (30) formed for the first signal line (L31A) and the second signal line (L31B) via an insulating material (10). The ground layer (30) includes a first ground layer (G31A) corresponding to a first region (D1) and a second ground layer (G31B) corresponding to a second region (D2). The first region (D1) is defined based on the first signal line (L31A) and has a first predetermined width (W31A). The second region (D2) is defined based on the second signal line (L31B) and has a second predetermined width (W31B).
    Type: Grant
    Filed: May 20, 2015
    Date of Patent: January 17, 2017
    Assignee: FUJIKURA LTD.
    Inventors: Hirohito Watanabe, Taiji Ogawa
  • Patent number: 9247651
    Abstract: To improve reliability by preventing separation of a sheet material attached on a flexible printed circuit, provided is a flexible printed circuit including a printed board body and a reinforcing board. A leaked portion of an adhesive agent is formed to leak in an outward direction relative to an end surface of the reinforcing board. The leaked portion adheres to part of the end surface of the reinforcing board to be continuous from a lower end of the end surface to form an inclined surface tapered in the outward direction. The leaked portion is formed such that a portion thereof that covers the end surface has an adhesion height hA, as measured from an adhesive surface of the reinforcing board, of greater than 0% and not greater than 80% of the thickness H1 of the reinforcing board.
    Type: Grant
    Filed: April 6, 2010
    Date of Patent: January 26, 2016
    Assignee: FUJIKURA LTD.
    Inventor: Hirohito Watanabe
  • Publication number: 20150342030
    Abstract: To suppress occurrence of a difference in transmission time due to a difference in length between signal lines, there is provided a printed wiring board having: an insulating substrate (10); a first signal line (L31A) that constitutes differential signal lines formed on the insulating substrate (10) and includes a curved portion; a second signal line (L31B) provided along the first signal line (L31A) and side by side inside the curved portion; and a ground layer (30) formed for the first signal line (L31A) and the second signal line (L31B) via an insulating material (10). The ground layer (30) includes a first ground layer (G31A) corresponding to a first region (D1) and a second ground layer (G31B) corresponding to a second region (D2). The first region (D1) is defined based on the first signal line (L31A) and has a first predetermined width (W31A). The second region (D2) is defined based on the second signal line (L31B) and has a second predetermined width (W31B).
    Type: Application
    Filed: May 20, 2015
    Publication date: November 26, 2015
    Applicant: FUJIKURA LTD.
    Inventors: Hirohito WATANABE, Taiji OGAWA
  • Publication number: 20150340751
    Abstract: To suppress occurrence of a difference in transmission time due to a difference in length between signal lines, there is provided a printed wiring board having: an insulating substrate (10); a first signal line (L31) formed on the insulating substrate (10); a second signal line (L32) having a shorter length than that of the first signal line (L31); and a ground layer (30) formed for the first signal line (L31) and the second signal line (L31) via an insulating material (10). The ground layer (30) includes a first ground layer (G31) corresponding to a first region (D1) and a second ground layer (G32) corresponding to a second region (D2). The first region (D1) is defined based on the first signal line (L31) and has a first predetermined width (W31). The second region (D2) is defined based on the second signal line (L32) and has a second predetermined width (W32). The first ground layer (G31) has a remaining ratio lower than a remaining ratio of the second ground layer (G32).
    Type: Application
    Filed: May 20, 2015
    Publication date: November 26, 2015
    Applicant: FUJIKURA LTD.
    Inventors: Hirohito WATANABE, Taiji OGAWA
  • Patent number: 9055676
    Abstract: A differential signal transmission circuit comprises: an insulating layer; two signal lines provided in parallel on one surface of the insulating layer; a GND line formed on each of outer sides of the two signal lines on the one surface of the insulating layer; and a wiring line layer formed on the other surface of the insulating layer, the differential signal transmission circuit being configured by a double-sided flexible printed circuit board, the signal lines, the GND line and the wiring line layer being formed by a semi-additive method on the insulating layer, and the signal line and the GND line being formed such that a distance S between the two signal lines is greater than a distance D between the signal line and the GND line.
    Type: Grant
    Filed: February 21, 2013
    Date of Patent: June 9, 2015
    Assignee: FUJIKURA LTD.
    Inventor: Hirohito Watanabe
  • Patent number: 9006579
    Abstract: A method of manufacturing a printed circuit board includes: forming a copper layer of an interconnection pattern on a base film; laminating a cover lay on the base film so as to expose a part of the copper layer from the cover lay and cover the copper layer by the cover lay; mechanically polishing at least the exposed portion of the copper layer; and performing a plating process on the exposed portion of the copper layer so as to form a plated layer on the copper layer, and the angles ?1 and ?2 between the polishing direction of the exposed portion of the copper layer and the bending lines C1 and C2 satisfy the following formula (1): 30°??1 and ?2?150°??(1).
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: April 14, 2015
    Assignee: Fujikura Ltd.
    Inventors: Masatoshi Inaba, Hiroshi Miyata, Hirohito Watanabe
  • Patent number: 8841976
    Abstract: The printed wiring board has a conductor of signal line 41 and two conductive lines 42 on one face of the first insulating layer 10 covered by a second insulating layer 20, while having a ground layer of the ground 30 potential on the opposite face thereof, when the dielectric tangent A of the second insulating layer (insulating layer A) 20 is larger than the dielectric tangent B of the first insulating layer (insulating layer B) 10, Relational Expression 1: (relative permittivity B)·(width (W41) of signal line(s) 41)/(thickness (T10) of first insulating layer (insulating layer B) 10)>(relative permittivity A)·{(thickness (T41) of signal line(s) 41)/(distance (S1) between signal line(s) 41 and one conductive line 42a)+(thickness (T41) of signal line(s) 41)/(distance (S2) between signal line(s) 41 and other conductive line 42b)+(thickness (T41) of signal lines 41)/(distance (S3) between pair of signal lines (41a and 41b)·2} is satisfied.
    Type: Grant
    Filed: January 9, 2012
    Date of Patent: September 23, 2014
    Assignee: Fujikura Ltd.
    Inventors: Taiji Ogawa, Hirohito Watanabe, Masazaku Sato
  • Patent number: 8809687
    Abstract: [Object]To provide a flexible printed board improved in bendability. [Means for solving]The flexible printed board 2 comprises: an insulating substrate 21; a circuit wiring 22 laid on the insulating substrate 21; a circuit protection layer 23 laid on the circuit wiring 22; a shield conductive layer 24 laid on the circuit protection layer 23; and a shield insulating layer 25 laid on the shield conductive layer 24, and is characterized by meeting the following Expression (1). 0.75?E2/E1?1.29??Expression (1) Note that E1 denotes the tensile elastic modulus of the shield conductive layer 24 and E2 denotes the tensile elastic modulus of the shield insulating layer 25.
    Type: Grant
    Filed: March 31, 2011
    Date of Patent: August 19, 2014
    Assignee: Fujikura Ltd.
    Inventor: Hirohito Watanabe
  • Patent number: 8574449
    Abstract: Quickly making changes to etching conditions suppresses the production yield of printed wiring boards from being deteriorated. Disclosed is a method comprising: an etching step that comprises: preparing a conductor-clad base material continuous in a certain direction, the conductor-clad base material (1) having an insulating layer and one or more conductive layers formed on main surfaces of the insulating layer; and subjecting a predetermined region of a conductor layer of one main surface of the conductor-clad base material (1) to an etching process thereby to form a wiring pattern (1a) to be of a product and an inspection pattern (1b) to be used for inspection; a measuring step that measures a line width of the inspection pattern after the etching step; and a control step that controls an etching condition in the etching step based on the measured line width.
    Type: Grant
    Filed: May 2, 2012
    Date of Patent: November 5, 2013
    Assignee: Fujikura Ltd.
    Inventors: Hirohito Watanabe, Taiji Ogawa, Eriko Tomonaga
  • Patent number: 8546696
    Abstract: A printed circuit board having a connection terminal which includes: an insulating substrate including first and second surfaces, and an end surface along an outline normal to an insertion direction of the connection terminal; at least one lead wiring layer formed on the first surface of the insulating substrate; an insulating protection film covering the lead wiring layer; at least one lead terminal layer constituting an end portion of the lead wiring layer, the lead terminal layer being formed into a strip, and having an end surface along the outline; a reinforcement body adhered on the second surface of the insulating substrate at a backside position of the lead terminal layer; wherein a distance between an outer surface of the lead terminal layer and an outer surface of the reinforcement body on the outline side is smaller than a distance therebetween on the lead wiring layer side.
    Type: Grant
    Filed: June 22, 2010
    Date of Patent: October 1, 2013
    Assignee: Fujikura Ltd.
    Inventor: Hirohito Watanabe
  • Publication number: 20130087370
    Abstract: A method of manufacturing a printed circuit board includes: forming a copper layer of an interconnection pattern on a base film; laminating a cover lay on the base film so as to expose a part of the copper layer from the cover lay and cover the copper layer by the cover lay; mechanically polishing at least the exposed portion of the copper layer; and performing a plating process on the exposed portion of the copper layer so as to form a plated layer on the copper layer, and the angles ?1 and ?2 between the polishing direction of the exposed portion of the copper layer and the bending lines C1 and C2 satisfy the following formula (1): 30[°]??1 and ?2?150[°]??(1).
    Type: Application
    Filed: September 14, 2012
    Publication date: April 11, 2013
    Applicant: FUJIKURA LTD.
    Inventors: Masatoshi INABA, Hiroshi MIYATA, Hirohito WATANABE
  • Publication number: 20120292085
    Abstract: Provided is a flexible printed circuit having a multilayered structure including three conductive layers. The flexible printed circuit includes: a first unit substrate formed of a first insulating layer made of liquid crystal polymer or fluorine resin and having a signal transmission circuit formed on one surface of the first insulating layer and a first conductive layer formed on the other surface thereof; a second unit substrate formed of a second insulating layer made of liquid crystal polymer or fluorine resin and having a second conductive layer formed on one surface of the second insulating layer; and an adhesive layer made of an epoxy thermal curing adhesive for bonding the first unit substrate and the second unit substrate in a state that the one surface of the first insulating layer is faced with the other surface of the second insulating layer.
    Type: Application
    Filed: April 25, 2012
    Publication date: November 22, 2012
    Applicant: FUJIKURA LTD.
    Inventor: Hirohito Watanabe
  • Publication number: 20120279050
    Abstract: Quickly making changes to etching conditions suppresses the production yield of printed wiring boards from being deteriorated. Disclosed is a method comprising: an etching step that comprises: preparing a conductor-clad base material continuous in a certain direction, the conductor-clad base material (1) having an insulating layer and one or more conductive layers formed on main surfaces of the insulating layer; and subjecting a predetermined region of a conductor layer of one main surface of the conductor-clad base material (1) to an etching process thereby to form a wiring pattern (1a) to be of a product and an inspection pattern (1b) to be used for inspection; a measuring step that measures a line width of the inspection pattern after the etching step; and a control step that controls an etching condition in the etching step based on the measured line width.
    Type: Application
    Filed: May 2, 2012
    Publication date: November 8, 2012
    Applicant: FUJIKURA LTD.
    Inventors: Hirohito WATANABE, Taiji OGAWA, Takaomi Tomonaga, Eriko TOMONAGA
  • Publication number: 20120205141
    Abstract: The printed wiring board has a conductor of signal line 41 and two conductive lines 42 on one face of the first insulating layer 10 covered by a second insulating layer 20, while having a ground layer of the ground 30 potential on the opposite face thereof, when the dielectric tangent A of the second insulating layer (insulating layer A) 20 is larger than the dielectric tangent B of the first insulating layer (insulating layer B) 10, Relational Expression 1: (relative permittivity B)·(width (W41) of signal line(s) 41)/(thickness (T10) of first insulating layer (insulating layer B) 10)>(relative permittivity A)·{(thickness (T41) of signal line(s) 41)/(distance (S1) between signal line(s) 41 and one conductive line 42a)+(thickness (T41) of signal line(s) 41)/(distance (S2) between signal line(s) 41 and other conductive line 42b)+(thickness (T41) of signal lines 41)/(distance (S3) between pair of signal lines (41a and 41b)·2} is satisfied.
    Type: Application
    Filed: January 9, 2012
    Publication date: August 16, 2012
    Applicant: FUJIKURA LTD.
    Inventors: Taiji OGAWA, Hirohito WATANABE, Masakazu SATO
  • Patent number: 8177561
    Abstract: A socket contact terminal for electrical connection between a connection portion formed of a metal conductor on a printed circuit board and a connection terminal of an IC package. The contact terminal comprises a metal terminal composed of a main columnar portion and arm portions on both sides and having an angular U shape and an elastomeric member attached to the metal terminal. A metal surface is exposed from the outer surface of each arm portion. The elastomeric member is firmly held between the arm portions of the metal terminal and exhibits a repulsive force when the arm portions are pressed in the direction that the arm portions approach each other.
    Type: Grant
    Filed: May 23, 2007
    Date of Patent: May 15, 2012
    Assignee: Fujikura Ltd.
    Inventors: Yasuhiro Ouchi, Shinichi Nikaido, Haruo Miyazawa, Hirohito Watanabe, Katsuya Yamagami
  • Publication number: 20110247863
    Abstract: [Object] To provide a flexible printed board improved in bendability. [Means for solving] The flexible printed board 2 comprises: an insulating substrate 21; a circuit wiring 22 laid on the insulating substrate 21; a circuit protection layer 23 laid on the circuit wiring 22; a shield conductive layer 24 laid on the circuit protection layer 23; and a shield insulating layer 25 laid on the shield conductive layer 24, and is characterized by meeting the following Expression (1). 0.75?E2/E1?1.29??Expression (1) Note that E1 denotes the tensile elastic modulus of the shield conductive layer 24 and E2 denotes the tensile elastic modulus of the shield insulating layer 25.
    Type: Application
    Filed: March 31, 2011
    Publication date: October 13, 2011
    Applicant: FUJIKURA LTD.
    Inventor: Hirohito WATANABE
  • Patent number: 7880215
    Abstract: A diffusion layer (102) is formed in the surface region of a semiconductor substrate (101). A control gate electrode (103) is formed on the substrate. An interlayer dielectric film (108) covers the entire surface of the substrate. A drain leader line (104) made of a semiconductor such as n-type polysilicon is led from the drain region, and a source leader line (107) is led from the source region through the interlayer dielectric film. The drain leader line is surrounded by an annular floating gate (105). In erase, for example, the control gate is set to a ground potential, and a positive voltage is applied to the drain leader line to remove electrons in the floating gate to the drain leader line. In write, positive voltages are applied to the control gate electrode and drain leader line to generate CHE and inject hot electrons into the floating gate. This allows to thin the gate insulating film of a flash memory, increase the degree of integration of a nonvolatile memory, and lower the driving voltage.
    Type: Grant
    Filed: November 16, 2005
    Date of Patent: February 1, 2011
    Assignee: NEC Corporation
    Inventors: Hirohito Watanabe, Motofumi Saitou, Hiroshi Sunamura