Abstract: To suppress occurrence of a difference in transmission time due to a difference in length between signal lines, there is provided a printed wiring board having: an insulating substrate (10); a first signal line (L31) formed on the insulating substrate (10); a second signal line (L32) having a shorter length than that of the first signal line (L31); and a ground layer (30) formed for the first signal line (L31) and the second signal line (L31) via an insulating material (10). The ground layer (30) includes a first ground layer (G31) corresponding to a first region (D1) and a second ground layer (G32) corresponding to a second region (D2). The first region (D1) is defined based on the first signal line (L31) and has a first predetermined width (W31). The second region (D2) is defined based on the second signal line (L32) and has a second predetermined width (W32). The first ground layer (G31) has a remaining ratio lower than a remaining ratio of the second ground layer (G32).

Abstract: To suppress occurrence of a difference in transmission time due to a difference in length between signal lines, there is provided a printed wiring board having: an insulating substrate (10); a first signal line (L31A) that constitutes differential signal lines formed on the insulating substrate (10) and includes a curved portion; a second signal line (L31B) provided along the first signal line (L31A) and side by side inside the curved portion; and a ground layer (30) formed for the first signal line (L31A) and the second signal line (L31B) via an insulating material (10). The ground layer (30) includes a first ground layer (G31A) corresponding to a first region (D1) and a second ground layer (G31B) corresponding to a second region (D2). The first region (D1) is defined based on the first signal line (L31A) and has a first predetermined width (W31A). The second region (D2) is defined based on the second signal line (L31B) and has a second predetermined width (W31B).

Abstract: To improve reliability by preventing separation of a sheet material attached on a flexible printed circuit, provided is a flexible printed circuit including a printed board body and a reinforcing board. A leaked portion of an adhesive agent is formed to leak in an outward direction relative to an end surface of the reinforcing board. The leaked portion adheres to part of the end surface of the reinforcing board to be continuous from a lower end of the end surface to form an inclined surface tapered in the outward direction. The leaked portion is formed such that a portion thereof that covers the end surface has an adhesion height hA, as measured from an adhesive surface of the reinforcing board, of greater than 0% and not greater than 80% of the thickness H1 of the reinforcing board.

Abstract: A differential signal transmission circuit comprises: an insulating layer; two signal lines provided in parallel on one surface of the insulating layer; a GND line formed on each of outer sides of the two signal lines on the one surface of the insulating layer; and a wiring line layer formed on the other surface of the insulating layer, the differential signal transmission circuit being configured by a double-sided flexible printed circuit board, the signal lines, the GND line and the wiring line layer being formed by a semi-additive method on the insulating layer, and the signal line and the GND line being formed such that a distance S between the two signal lines is greater than a distance D between the signal line and the GND line.

Abstract: A method of manufacturing a printed circuit board includes: forming a copper layer of an interconnection pattern on a base film; laminating a cover lay on the base film so as to expose a part of the copper layer from the cover lay and cover the copper layer by the cover lay; mechanically polishing at least the exposed portion of the copper layer; and performing a plating process on the exposed portion of the copper layer so as to form a plated layer on the copper layer, and the angles ?1 and ?2 between the polishing direction of the exposed portion of the copper layer and the bending lines C1 and C2 satisfy the following formula (1): 30°??1 and ?2?150°??(1).

Abstract: The printed wiring board has a conductor of signal line 41 and two conductive lines 42 on one face of the first insulating layer 10 covered by a second insulating layer 20, while having a ground layer of the ground 30 potential on the opposite face thereof, when the dielectric tangent A of the second insulating layer (insulating layer A) 20 is larger than the dielectric tangent B of the first insulating layer (insulating layer B) 10, Relational Expression 1: (relative permittivity B)·(width (W41) of signal line(s) 41)/(thickness (T10) of first insulating layer (insulating layer B) 10)>(relative permittivity A)·{(thickness (T41) of signal line(s) 41)/(distance (S1) between signal line(s) 41 and one conductive line 42a)+(thickness (T41) of signal line(s) 41)/(distance (S2) between signal line(s) 41 and other conductive line 42b)+(thickness (T41) of signal lines 41)/(distance (S3) between pair of signal lines (41a and 41b)·2} is satisfied.

Abstract: [Object]To provide a flexible printed board improved in bendability. [Means for solving]The flexible printed board 2 comprises: an insulating substrate 21; a circuit wiring 22 laid on the insulating substrate 21; a circuit protection layer 23 laid on the circuit wiring 22; a shield conductive layer 24 laid on the circuit protection layer 23; and a shield insulating layer 25 laid on the shield conductive layer 24, and is characterized by meeting the following Expression (1). 0.75?E2/E1?1.29??Expression (1) Note that E1 denotes the tensile elastic modulus of the shield conductive layer 24 and E2 denotes the tensile elastic modulus of the shield insulating layer 25.

Abstract: Quickly making changes to etching conditions suppresses the production yield of printed wiring boards from being deteriorated. Disclosed is a method comprising: an etching step that comprises: preparing a conductor-clad base material continuous in a certain direction, the conductor-clad base material (1) having an insulating layer and one or more conductive layers formed on main surfaces of the insulating layer; and subjecting a predetermined region of a conductor layer of one main surface of the conductor-clad base material (1) to an etching process thereby to form a wiring pattern (1a) to be of a product and an inspection pattern (1b) to be used for inspection; a measuring step that measures a line width of the inspection pattern after the etching step; and a control step that controls an etching condition in the etching step based on the measured line width.

Abstract: A printed circuit board having a connection terminal which includes: an insulating substrate including first and second surfaces, and an end surface along an outline normal to an insertion direction of the connection terminal; at least one lead wiring layer formed on the first surface of the insulating substrate; an insulating protection film covering the lead wiring layer; at least one lead terminal layer constituting an end portion of the lead wiring layer, the lead terminal layer being formed into a strip, and having an end surface along the outline; a reinforcement body adhered on the second surface of the insulating substrate at a backside position of the lead terminal layer; wherein a distance between an outer surface of the lead terminal layer and an outer surface of the reinforcement body on the outline side is smaller than a distance therebetween on the lead wiring layer side.

Abstract: Provided is a flexible printed circuit having a multilayered structure including three conductive layers. The flexible printed circuit includes: a first unit substrate formed of a first insulating layer made of liquid crystal polymer or fluorine resin and having a signal transmission circuit formed on one surface of the first insulating layer and a first conductive layer formed on the other surface thereof; a second unit substrate formed of a second insulating layer made of liquid crystal polymer or fluorine resin and having a second conductive layer formed on one surface of the second insulating layer; and an adhesive layer made of an epoxy thermal curing adhesive for bonding the first unit substrate and the second unit substrate in a state that the one surface of the first insulating layer is faced with the other surface of the second insulating layer.

Abstract: A socket contact terminal for electrical connection between a connection portion formed of a metal conductor on a printed circuit board and a connection terminal of an IC package. The contact terminal comprises a metal terminal composed of a main columnar portion and arm portions on both sides and having an angular U shape and an elastomeric member attached to the metal terminal. A metal surface is exposed from the outer surface of each arm portion. The elastomeric member is firmly held between the arm portions of the metal terminal and exhibits a repulsive force when the arm portions are pressed in the direction that the arm portions approach each other.

Abstract: A diffusion layer (102) is formed in the surface region of a semiconductor substrate (101). A control gate electrode (103) is formed on the substrate. An interlayer dielectric film (108) covers the entire surface of the substrate. A drain leader line (104) made of a semiconductor such as n-type polysilicon is led from the drain region, and a source leader line (107) is led from the source region through the interlayer dielectric film. The drain leader line is surrounded by an annular floating gate (105). In erase, for example, the control gate is set to a ground potential, and a positive voltage is applied to the drain leader line to remove electrons in the floating gate to the drain leader line. In write, positive voltages are applied to the control gate electrode and drain leader line to generate CHE and inject hot electrons into the floating gate. This allows to thin the gate insulating film of a flash memory, increase the degree of integration of a nonvolatile memory, and lower the driving voltage.

Abstract: A semiconductor device includes first and second active regions on a semiconductor substrate, separated by an element isolation region; a line-shaped electrode disposed from over the first to over the second active region via the element isolation region; first and second FETs including a gate insulating film on the first and second active regions, respectively, a gate electrode composed of the line-shaped electrode and a source/drain region. Parts of the line-shaped electrode over the first and second active regions are formed of different materials. The line-shaped electrode includes a diffusion restraining region having thickness in a direction perpendicular to the substrate thinner than that over the first and second active regions. The diffusion restraining region is over the element isolation region and spans the whole width of the line-shaped electrode in the gate length direction.

Abstract: A semiconductor device 100 includes a silicon substrate 102, an N-type MOSFET 118 including a first high dielectric constant film 111 and a polycrystalline silicon film 114 on the silicon substrate 102, and a P-type MOSFET 120 including a second high dielectric constant film 12 and a polycrystalline silicon film 114 juxtaposed to N-type MOSFET 118 on the silicon substrate 102. The second high dielectric constant film 112 is formed to have the film thickness thinner than the film thickness of the first high dielectric constant film 111. The first high dielectric constant film 111 and the second high dielectric constant film 112 contains one or more element(s) selected from Hf and Zr.

Abstract: The task of the present invention is to enable formation of a gate insulating film structure having a good-quality interface between a silicon oxide film and silicon in an interface between a high dielectric constant thin film and a silicon substrate to provide a semiconductor device and a semiconductor manufacturing method which are capable of improving interface electrical characteristics, which has been a longstanding task in practical use of a high dielectric constant insulating film. A metal layer deposition process and a heat treatment process which supply metal elements constituting a high dielectric constant film on a surface of a base silicon oxide film 103 allow the metal elements to be diffused into the base silicon oxide film 103 to thereby form an insulating film structure 105 as a gate insulating film, after forming the base silicon oxide film 103 on a surface of a silicon substrate 101.

Abstract: A socket contact terminal for electrical connection between a connection portion formed of a metal conductor on a printed circuit board and a connection terminal of an IC package. The contact terminal comprises a metal terminal composed of a main columnar portion and arm portions on both sides and having an angular U shape and an elastomeric member attached to the metal terminal. A metal surface is exposed from the outer surface of each arm portion. The elastomeric member is firmly held between the arm portions of the metal terminal and exhibits a repulsive force when the arm portions are pressed in the direction that the arm portions approach each other.

Abstract: A semiconductor device includes first and second active regions on a semiconductor substrate, separated by an element isolation region; a line-shaped electrode disposed from over the first to over the second active region via the element isolation region; first and second FETs including a gate insulating film on the first and second active regions, respectively, a gate electrode composed of the line-shaped electrode and a source/drain region. Parts of the line-shaped electrode over the first and second active regions are formed of different materials. The line-shaped electrode includes a diffusion restraining region having thickness in a direction perpendicular to the substrate thinner than that over the first and second active regions. The diffusion restraining region is over the element isolation region and spans the whole width of the line-shaped electrode in the gate length direction.

Abstract: A semiconductor device provided with a MIS type field effect transistor comprising a silicon substrate, a gate insulating film having a high-dielectric-constant metal oxide film which is formed on the silicon substrate via a silicon containing insulating film, a silicon-containing gate electrode formed on the gate insulating film, and a sidewall including, as a constituting material, silicon oxide on a lateral face side of the gate electrode, wherein a silicon nitride film is interposed between the sidewall and at least the lateral face of the gate electrode. This semiconductor device, although having a fine structure with a small gate length, is capable of low power consumption and fast operation.

Abstract: A diffusion layer (102) is formed in the surface region of a semiconductor substrate (101). A control gate electrode (103) is formed on the substrate. An interlayer dielectric film (108) covers the entire surface of the substrate. A drain leader line (104) made of a semiconductor such as n-type polysilicon is led from the drain region, and a source leader line (107) is led from the source region through the interlayer dielectric film. The drain leader line is surrounded by an annular floating gate (105). In erase, for example, the control gate is set to a ground potential, and a positive voltage is applied to the drain leader line to remove electrons in the floating gate to the drain leader line. In write, positive voltages are applied to the control gate electrode and drain leader line to generate CHE and inject hot electrons into the floating gate. This allows to thin the gate insulating film of a flash memory, increase the degree of integration of a nonvolatile memory, and lower the driving voltage.

Abstract: A semiconductor device 100 comprises a silicon substrate 102, an N-type MOSFET 118 including a high concentration-high dielectric constant film 108b formed on the silicon substrate 102 and a polycrystalline silicon film 114, and a P-type MOSFET 120 including a low concentration-high dielectric constant film 108a and a polycrystalline silicon film 114 formed on the semiconductor substrate 102 to be juxtaposed to the N-type MOSFET 118. The low concentration-high dielectric constant film 108a and the high concentration-high dielectric constant film 108b are composed of a material containing one or more element (s) selected from a group consisting of Hf and Zr. The concentration of the above-described metallic element contained in the low concentration-high dielectric constant film 108a is lower than that contained in the high concentration-high dielectric constant film 108b.