Patents by Inventor Hirohito Watanabe

Hirohito Watanabe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100319972
    Abstract: A printed circuit board having a connection terminal which includes: an insulating substrate including first and second surfaces, and an end surface along an outline normal to an insertion direction of the connection terminal; at least one lead wiring layer formed on the first surface of the insulating substrate; an insulating protection film covering the lead wiring layer; at least one lead terminal layer constituting an end portion of the lead wiring layer, the lead terminal layer being formed into a strip, and having an end surface along the outline; a reinforcement body adhered on the second surface of the insulating substrate at a backside position of the lead terminal layer; wherein a distance between an outer surface of the lead terminal layer and an outer surface of the reinforcement body on the outline side is smaller than a distance therebetween on the lead wiring layer side.
    Type: Application
    Filed: June 22, 2010
    Publication date: December 23, 2010
    Applicant: FUJIKURA LTD.
    Inventor: Hirohito WATANABE
  • Publication number: 20100307797
    Abstract: To improve reliability by preventing separation of a sheet material attached on a flexible printed circuit, provided is a flexible printed circuit including a printed board body and a reinforcing board. A leaked portion of an adhesive agent is formed to leak in an outward direction relative to an end surface of the reinforcing board. The leaked portion adheres to part of the end surface of the reinforcing board to be continuous from a lower end of the end surface to form an inclined surface tapered in the outward direction. The leaked portion is formed such that a portion thereof that covers the end surface has an adhesion height hA, as measured from an adhesive surface of the reinforcing board, of greater than 0% and not greater than 80% of the thickness H1 of the reinforcing board.
    Type: Application
    Filed: April 6, 2010
    Publication date: December 9, 2010
    Applicant: FUJIKURA LTD.
    Inventor: Hirohito WATANABE
  • Patent number: 7838945
    Abstract: A semiconductor device includes first and second active regions on a semiconductor substrate, separated by an element isolation region; a line-shaped electrode disposed from over the first to over the second active region via the element isolation region; first and second FETs including a gate insulating film on the first and second active regions, respectively, a gate electrode composed of the line-shaped electrode and a source/drain region. Parts of the line-shaped electrode over the first and second active regions are formed of different materials. The line-shaped electrode includes a diffusion restraining region having thickness in a direction perpendicular to the substrate thinner than that over the first and second active regions. The diffusion restraining region is over the element isolation region and spans the whole width of the line-shaped electrode in the gate length direction.
    Type: Grant
    Filed: October 18, 2006
    Date of Patent: November 23, 2010
    Assignee: NEC Corporation
    Inventors: Motofumi Saitoh, Hirohito Watanabe
  • Patent number: 7759744
    Abstract: A semiconductor device 100 includes a silicon substrate 102, an N-type MOSFET 118 including a first high dielectric constant film 111 and a polycrystalline silicon film 114 on the silicon substrate 102, and a P-type MOSFET 120 including a second high dielectric constant film 12 and a polycrystalline silicon film 114 juxtaposed to N-type MOSFET 118 on the silicon substrate 102. The second high dielectric constant film 112 is formed to have the film thickness thinner than the film thickness of the first high dielectric constant film 111. The first high dielectric constant film 111 and the second high dielectric constant film 112 contains one or more element(s) selected from Hf and Zr.
    Type: Grant
    Filed: May 16, 2005
    Date of Patent: July 20, 2010
    Assignees: NEC Electronics Corporation, NEC Corporation
    Inventors: Naohiko Kimizuka, Kiyotaka Imai, Yuri Masuoka, Toshiyuki Iwamoto, Motofumi Saitoh, Hirohito Watanabe, Masayuki Terai
  • Patent number: 7679148
    Abstract: The task of the present invention is to enable formation of a gate insulating film structure having a good-quality interface between a silicon oxide film and silicon in an interface between a high dielectric constant thin film and a silicon substrate to provide a semiconductor device and a semiconductor manufacturing method which are capable of improving interface electrical characteristics, which has been a longstanding task in practical use of a high dielectric constant insulating film. A metal layer deposition process and a heat treatment process which supply metal elements constituting a high dielectric constant film on a surface of a base silicon oxide film 103 allow the metal elements to be diffused into the base silicon oxide film 103 to thereby form an insulating film structure 105 as a gate insulating film, after forming the base silicon oxide film 103 on a surface of a silicon substrate 101.
    Type: Grant
    Filed: July 16, 2003
    Date of Patent: March 16, 2010
    Assignee: NEC Corporation
    Inventors: Heiji Watanabe, Hirohito Watanabe, Toru Tatsumi, Shinji Fujieda
  • Publication number: 20090250256
    Abstract: A socket contact terminal for electrical connection between a connection portion formed of a metal conductor on a printed circuit board and a connection terminal of an IC package. The contact terminal comprises a metal terminal composed of a main columnar portion and arm portions on both sides and having an angular U shape and an elastomeric member attached to the metal terminal. A metal surface is exposed from the outer surface of each arm portion. The elastomeric member is firmly held between the arm portions of the metal terminal and exhibits a repulsive force when the arm portions are pressed in the direction that the arm portions approach each other.
    Type: Application
    Filed: May 23, 2007
    Publication date: October 8, 2009
    Applicant: FUJIKURA, LTD.
    Inventors: Yasuhiro Ouchi, Shinichi Nikaido, Haruo Miyazawa, Hirohito Watanabe, Katsuya Yamagami
  • Publication number: 20090096032
    Abstract: A semiconductor device includes first and second active regions on a semiconductor substrate, separated by an element isolation region; a line-shaped electrode disposed from over the first to over the second active region via the element isolation region; first and second FETs including a gate insulating film on the first and second active regions, respectively, a gate electrode composed of the line-shaped electrode and a source/drain region. Parts of the line-shaped electrode over the first and second active regions are formed of different materials. The line-shaped electrode includes a diffusion restraining region having thickness in a direction perpendicular to the substrate thinner than that over the first and second active regions. The diffusion restraining region is over the element isolation region and spans the whole width of the line-shaped electrode in the gate length direction.
    Type: Application
    Filed: October 18, 2006
    Publication date: April 16, 2009
    Applicant: NEC CORPORATION
    Inventors: Motofumi Saitoh, Hirohito Watanabe
  • Publication number: 20080203500
    Abstract: A semiconductor device provided with a MIS type field effect transistor comprising a silicon substrate, a gate insulating film having a high-dielectric-constant metal oxide film which is formed on the silicon substrate via a silicon containing insulating film, a silicon-containing gate electrode formed on the gate insulating film, and a sidewall including, as a constituting material, silicon oxide on a lateral face side of the gate electrode, wherein a silicon nitride film is interposed between the sidewall and at least the lateral face of the gate electrode. This semiconductor device, although having a fine structure with a small gate length, is capable of low power consumption and fast operation.
    Type: Application
    Filed: February 15, 2008
    Publication date: August 28, 2008
    Applicant: NEC CORPORATION
    Inventors: Takashi Ogura, Nobuyuki Ikarashi, Toshiyuki Iwamoto, Hirohito Watanabe
  • Publication number: 20080144377
    Abstract: A diffusion layer (102) is formed in the surface region of a semiconductor substrate (101). A control gate electrode (103) is formed on the substrate. An interlayer dielectric film (108) covers the entire surface of the substrate. A drain leader line (104) made of a semiconductor such as n-type polysilicon is led from the drain region, and a source leader line (107) is led from the source region through the interlayer dielectric film. The drain leader line is surrounded by an annular floating gate (105). In erase, for example, the control gate is set to a ground potential, and a positive voltage is applied to the drain leader line to remove electrons in the floating gate to the drain leader line. In write, positive voltages are applied to the control gate electrode and drain leader line to generate CHE and inject hot electrons into the floating gate. This allows to thin the gate insulating film of a flash memory, increase the degree of integration of a nonvolatile memory, and lower the driving voltage.
    Type: Application
    Filed: November 16, 2005
    Publication date: June 19, 2008
    Inventors: Hirohito Watanabe, Motofumi Saitou, Hiroshi Sunamura
  • Patent number: 7238996
    Abstract: A semiconductor device 100 comprises a silicon substrate 102, an N-type MOSFET 118 including a high concentration-high dielectric constant film 108b formed on the silicon substrate 102 and a polycrystalline silicon film 114, and a P-type MOSFET 120 including a low concentration-high dielectric constant film 108a and a polycrystalline silicon film 114 formed on the semiconductor substrate 102 to be juxtaposed to the N-type MOSFET 118. The low concentration-high dielectric constant film 108a and the high concentration-high dielectric constant film 108b are composed of a material containing one or more element (s) selected from a group consisting of Hf and Zr. The concentration of the above-described metallic element contained in the low concentration-high dielectric constant film 108a is lower than that contained in the high concentration-high dielectric constant film 108b.
    Type: Grant
    Filed: May 16, 2005
    Date of Patent: July 3, 2007
    Assignees: NEC Electronics Corporation, NEC Corporation
    Inventors: Naohiko Kimizuka, Kiyotaka Imai, Yuri Masuoka, Toshiyuki Iwamoto, Motofumi Saitoh, Hirohito Watanabe, Ayuka Tada
  • Patent number: 7072554
    Abstract: A distinctive optical fiber comprises an optical fiber core, distinctive layers, and a colored layer. A plurality of the distinctive layers including fine drops of ink having a specific particle size is disposed intermittently on the optical fiber core in the longitudinal direction of the optical fiber core. The colored layer is disposed on the distinctive layers and on the optical fiber core on which the distinctive layers are not disposed. The following five requirements are required for obtaining the distinctive optical fiber excellent in distinctiveness and with low transmission loss. The thickness of the colored layer is chosen so as to be larger than or equal to 2 ?m and smaller than or equal to 10 ?m. The thickness of the distinctive layers is chosen so as to be larger than or equal to 0.5 ?m and smaller than or equal to 2.5 ?m. The length of the distinctive layers is chosen so as to be larger than or equal to 1 mm and smaller than or equal to 15 mm.
    Type: Grant
    Filed: July 8, 2003
    Date of Patent: July 4, 2006
    Assignee: Fujikura Ltd.
    Inventors: Hirohito Watanabe, Keiko Mitsuhashi, Tsuyoshi Shimomichi, Keiji Ohashi
  • Publication number: 20060131670
    Abstract: A semiconductor device provided with a MIS type field effect transistor comprising a silicon substrate, a gate insulating film having a high-dielectric-constant metal oxide film which is formed on the silicon substrate via a silicon containing insulating film, a silicon-containing gate electrode formed on the gate insulating film, and a sidewall including, as a constituting material, silicon oxide on a lateral face side of the gate electrode, wherein a silicon nitride film is interposed between the sidewall and at least the lateral face of the gate electrode. This semiconductor device, although having a fine structure with a small gate length, is capable of low power consumption and fast operation.
    Type: Application
    Filed: April 26, 2004
    Publication date: June 22, 2006
    Inventors: Takashi Ogura, Nobuyuki Ikarashi, Toshiyuki Iwamoto, Hirohito Watanabe
  • Publication number: 20050263802
    Abstract: A semiconductor device 100 comprises a silicon substrate 102, an N-type MOSFET 118 including a high concentration-high dielectric constant film 108b formed on the silicon substrate 102 and a polycrystalline silicon film 114, and a P-type MOSFET 120 including a low concentration-high dielectric constant film 108a and a polycrystalline silicon film 114 formed on the semiconductor substrate 102 to be juxtaposed to the N-type MOSFET 118. The low concentration-high dielectric constant film 108a and the high concentration-high dielectric constant film 108b are composed of a material containing one or more element (s) selected from a group consisting of Hf and Zr. The concentration of the above-described metallic element contained in the low concentration-high dielectric constant film 108a is lower than that contained in the high concentration-high dielectric constant film 108b.
    Type: Application
    Filed: May 16, 2005
    Publication date: December 1, 2005
    Applicants: NEC ELECTRONICS CORPORATION, NEC CORPORATION
    Inventors: Naohiko Kimizuka, Kiyotaka Imai, Yuri Masuoka, Toshiyuki Iwamoto, Motofumi Saitoh, Hirohito Watanabe, Ayuka Tada
  • Publication number: 20050253181
    Abstract: The semiconductor device 100 comprises a silicon substrate 102, an N-type MOSFET 118 including a first high dielectric constant film 111 and a polycrystalline silicon film 114 formed on the silicon substrate 102, and a P-type MOSFET 120 including a second high dielectric constant film 112 and a polycrystalline silicon film 114 juxtaposed to N-type MOSFET 118 on the silicon substrate 102. The second high dielectric constant film 112 is formed to have the film thickness thinner than the film thickness of the first high dielectric constant film 111. The first high dielectric constant film 111 and the second high dielectric constant film 112 contains one or more element(s) selected from a group consisting of Hf and Zr.
    Type: Application
    Filed: May 16, 2005
    Publication date: November 17, 2005
    Applicants: NEC ELECTRONICS CORPORATION, NEC CORPORATION
    Inventors: Naohiko Kimizuka, Kiyotaka Imai, Yuri Masuoka, Toshiyuki Iwamoto, Motofumi Saitoh, Hirohito Watanabe, Masayuki Terai
  • Publication number: 20050233526
    Abstract: The task of the present invention is to enable formation of a gate insulating film structure having a good-quality interface between a silicon oxide film and silicon in an interface between a high dielectric constant thin film and a silicon substrate to provide a semiconductor device and a semiconductor manufacturing method which are capable of improving interface electrical characteristics, which has been a longstanding task in practical use of a high dielectric constant insulating film. A metal layer deposition process and a heat treatment process which supply metal elements constituting a high dielectric constant film on a surface of a base silicon oxide film 103 allow the metal elements to be diffused into the base silicon oxide film 103 to thereby form an insulating film structure 105 as a gate insulating film, after forming the base silicon oxide film 103 on a surface of a silicon substrate 101.
    Type: Application
    Filed: July 16, 2003
    Publication date: October 20, 2005
    Inventors: Heiji Watanabe, Hirohito Watanabe, Toru Tatsumi, Shinji Fujieda
  • Patent number: 6853782
    Abstract: An optical fiber drop cable includes an optical element portion having an optical fiber core wire and a pair of first tension members disposed parallel to the optical fiber core wire on both sides thereof in a sandwiching manner. The optical fiber core wire and the pair of first tension members are coated with a cable sheath. A long-scale cable support wire portion has a second tension member coated with a sheath. The optical element portion and the cable support wire portion are adhered parallel to each other. The first tension members are composed of a nonconductive material. A flexural rigidity of the optical element portion is in a range from 80 to 500 Nmm2.
    Type: Grant
    Filed: July 15, 2002
    Date of Patent: February 8, 2005
    Assignee: Fujikura Ltd.
    Inventors: Kazunaga Kobayashi, Masahiro Kusakari, Matsuhiro Miyamoto, Hirohito Watanabe, Keiji Ohashi
  • Patent number: 6804442
    Abstract: An improved optical fiber is described. The optical fiber comprises: a fiber glass structure; a first jacket layer made of a soft curable resin and directly covering the external surface of said fiber glass structure; and a second jacket layer made of a rigid curable resin and covering the external surface of said fiber glass structure through said first jacket layer. The mechanical factors of said fiber glass structure, the mechanical factors of said first jacket layer and the mechanical factors of said second jacket layer are selected in order that the Young's modulus of said first jacket layer is larger than the average tensile stress (&sgr;r+&sgr;&thgr;+&sgr;z)/3 as applied to said first jacket layer 5 while the resin temperature of UV curable resins largely falls from the temperature when the rigid UV curable resin starts hardening to the temperature when the hardening is finished.
    Type: Grant
    Filed: June 2, 2003
    Date of Patent: October 12, 2004
    Assignee: Fujikura Ltd.
    Inventors: Hirohito Watanabe, Keiji Ohashi
  • Publication number: 20040028366
    Abstract: A distinctive optical fiber comprises an optical fiber core, distinctive layers, and a colored layer. A plurality of the distinctive layers including fine drops of ink having a specific particle size is disposed intermittently on the optical fiber core in the longitudinal direction of the optical fiber core. The colored layer is disposed on the distinctive layers and on the optical fiber core on which the distinctive layers are not disposed. The following five requirements are required for obtaining the distinctive optical fiber excellent in distinctiveness and with low transmission loss. The thickness of the colored layer is chosen so as to be larger than or equal to 2 &mgr;m and smaller than or equal to 10 &mgr;m. The thickness of the distinctive layers is chosen so as to be larger than or equal to 0.5 &mgr;m and smaller than or equal to 2.5 &mgr;m. The length of the distinctive layers is chosen so as to be larger than or equal to 1 mm and smaller than or equal to 15 mm.
    Type: Application
    Filed: July 8, 2003
    Publication date: February 12, 2004
    Applicant: FUJIKURA LTD.
    Inventors: Hirohito Watanabe, Keiko Mitsuhashi, Tsuyoshi Shimomichi, Keiji Ohashi
  • Publication number: 20030072545
    Abstract: A method for fabricating a drop cable includes the step of providing a strength member including a yarn including a non-conductive and tensile strength fiber. The method includes the step of arranging a core including an optical fiber side-by-side the strength member. The method includes the step of arranging a messenger wire side-by-side the core. The method includes the step of extruding the strength member, the core, and the messenger wire together for sheathing.
    Type: Application
    Filed: August 7, 2002
    Publication date: April 17, 2003
    Applicant: FUJIKURA LTD.
    Inventors: Masahiro Kusakari, Kazunaga Kobayashi, Shimei Tanaka, Hirohito Watanabe
  • Patent number: 6515322
    Abstract: A nonvolatile semiconductor memory comprises a silicon substrate, a gate electrode formed through a gate insulator film on a principal surface of the semiconductor substrate, a pair of source/drain regions formed in a principal surface region of the semiconductor substrate to locate the gate electrode between the pair of source/drain regions. The gate insulator film is formed of a silicon oxide and/or silicon nitride film in contact with the principal surface of the semiconductor substrate, and a lead germanate film which is formed on the silicon oxide and/or silicon nitride film and which is a ferroelectric having a dielectric constant of not larger than 50.
    Type: Grant
    Filed: May 20, 1996
    Date of Patent: February 4, 2003
    Assignee: NEC Corporation
    Inventor: Hirohito Watanabe