Patents by Inventor Hiroji Kawai
Hiroji Kawai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20020096692Abstract: Disclosed herein is an insulating nitride layer suitable for group III-V nitride semiconductor devices. It has a high resistance and good insulating properties and hence it electrically isolates elements, without the active layer decreasing in conductivity. Disclosed also herein is a process for forming said nitride layer and a semiconductor device having said nitride layer for improved characteristic properties. The semiconductor device is an AlGaN/GaN HEMT or the like which has a GaN active layer and an insulating nitride layer formed thereon from a group III-V nitride compound semiconductor heavily doped mostly with a group IIB element (particularly Zn) in an amount not less than 1×1017/cm3.Type: ApplicationFiled: August 8, 2001Publication date: July 25, 2002Inventors: Fumihiko Nakamura, Hisayoshi Kuramochi, Hiroji Kawai
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Publication number: 20020088979Abstract: A semiconductor crystal layer composed of GaN is grown on a base substrate composed of sapphire sandwiching a separating layer composed of AlN and a buffer layer composed of GaN. The separating layers and the buffer layers are distributed in the form of lines, and a flow-through hole for an etchant is formed in the side of these layers sandwiching an anti-growing film composed of SiO2. Thus, the etchant flows through the flow-through hole, the anti-growing film and the separating layer are etched, and the base substrate is easily isolated.Type: ApplicationFiled: March 15, 2002Publication date: July 11, 2002Inventor: Hiroji Kawai
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Patent number: 6413312Abstract: A new and improved method for growing a p-type nitride III-V compound semiconductor is provided which can produce a p-type nitride compound semiconductors having a high carrier concentration, without the need for annealing to activate impurities after growth. In a preferred embodiment, a p-type nitride compound semiconductor, such as p-type GaN, is grown by metal organic chemical vapor deposition methods using a nitrogen source material which does not release hydrogen during release of nitrogen and the semiconductor is grown in an inactive gas. The nitrogen source materials may be selected from nitrogen compounds that contain hydrogen radicals and alkyl radicals and/or phenyl radicals provided that the total amount of hydrogen radicals is less than or equal to the sum total of alkyl radicals and phenyl radicals present in the nitrogen compound used as the nitrogen source material.Type: GrantFiled: January 3, 2000Date of Patent: July 2, 2002Assignee: Sony CorporationInventors: Hiroji Kawai, Tsunenori Asatsuma, Fumihiko Nakamura
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Patent number: 6362016Abstract: A luminous intensity of a semiconductor light emitting device having a multi-layer structure formed of nitride group III-V compound semiconductors is improved by having a thickness d of a light emitting layer (active layer) of the semiconductor light emitting device having a multi-layer structure of nitride group III-V compound semiconductors ranging from 0.3 nm to 1.5 nm.Type: GrantFiled: April 25, 2000Date of Patent: March 26, 2002Assignee: Sony CorporationInventors: Kenji Funato, Tsunenori Asatsuma, Hiroji Kawai
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Publication number: 20010048114Abstract: There are provided a semiconductor substrate and a semiconductor laser using the semiconductor substrate which promises smooth and optically excellent cleaved surfaces and is suitable for fabricating semiconductor lasers using nitride III-V compound semiconductors. Using a semiconductor substrate, such as GaN substrate, having a major surface substantially normal to a {0001}-oriented face, e.g. {01-10}-oriented face or {11-20}-oriented face, or offset within ±5° from these faces, nitride III-V compound semiconductor layers are epitaxially grown on the substrate to form a laser structure. To make cavity edges, the GaN substrate is cleaved together with the overlying III-V compound semiconductor layers along high-cleavable {0001}-oriented faces.Type: ApplicationFiled: June 2, 1998Publication date: December 6, 2001Inventors: ETSUO MORITA, MASOA IKEDA, HIROJI KAWAI
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Publication number: 20010040245Abstract: When a device using GaN semiconductors is made on a hard and chemically stable single-crystal substrate such as sapphire substrate or SiC substrate, a semiconductor device and its manufacturing method ensure high-power output or high-frequency operation of the device by thinning the substrate or making a via hole in the substrate. When a light emitting device using GaN semiconductors is made on a non-conductive single-crystal substrate such as sapphire substrate, the semiconductor device and its manufacturing method reduce the operation voltage of the light emitting device by making a via hole to the substrate. More specifically, after making a GaN FET by growing GaN semiconductor layers on the surface of a sapphire substrate, the bottom surface of the sapphire substrate is processed by lapping, using an abrasive liquid containing a diamond granular abrasive material and reducing the grain size of the abrasive material in some steps, to reduce the thickness of the sapphire substrate to 100 &mgr;m or less.Type: ApplicationFiled: January 24, 2001Publication date: November 15, 2001Inventor: Hiroji Kawai
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Publication number: 20010035580Abstract: When a device using GaN semiconductors is made on a hard and chemically stable single-crystal substrate such as sapphire substrate or SiC substrate, a semiconductor device and its manufacturing method ensure high-power output or high-frequency operation of the device by thinning the substrate or making a via hole in the substrate. When a light emitting device using GaN semiconductors is made on a non-conductive single-crystal substrate such as sapphire substrate, the semiconductor device and its manufacturing method reduce the operation voltage of the light emitting device by making a via hole to the substrate. More specifically, after making a GaN FET by growing GaN semiconductor layers on the surface of a sapphire substrate, the bottom surface of the sapphire substrate is processed by lapping, using an abrasive liquid containing a diamond granular abrasive material and reducing the grain size of the abrasive material in some steps, to reduce the thickness of the sapphire substrate to 100 &mgr;m or less.Type: ApplicationFiled: January 24, 2001Publication date: November 1, 2001Inventor: Hiroji Kawai
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Patent number: 6281032Abstract: In a semiconductor device manufacturing method capable of manufacturing semiconductor lasers, light emitting diodes or electron transport devices using nitride III-V compound semiconductors with a high productivity, a GaN semiconductor laser wafer is prepared in which a plurality of semiconductor lasers are formed on an AlGaInN semiconductor layer on a c-face sapphire substrate and separated from each other by grooves deep enough to reach the c-face sapphire substrate, and a p-side electrode and an n-side electrode are formed in each semiconductor laser. The GaN semiconductor laser wafer is bonded to a photo-diode built-in Si wafer having formed a photo diode for monitoring light outputs and solder electrodes in each pellet by positioning the p-side electrode and the n-side electrode in alignment with the solder electrodes, respectively.Type: GrantFiled: April 14, 1999Date of Patent: August 28, 2001Assignee: Sony CorporationInventors: Osamu Matsuda, Toshimasa Kobayashi, Norikazu Nakayama, Hiroji Kawai
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Patent number: 6239033Abstract: After making a GaN FET by growing GaN semiconductor layers on the surface of a sapphire substrate, the bottom surface of the sapphire substrate is processed by lapping, using an abrasive liquid containing a diamond granular abrasive material and reducing the grain size of the abrasive material in some steps, to reduce the thickness of the sapphire substrate to 100 &mgr;m or less. Thereafter, the bottom surface of the sapphire substrate is processed by etching using an etchant of phosphoric acid or phosphoric acid/sulfuric acid mixed liquid to remove a strained layer by lapping. Then, after making a via hole by etching the bottom surface of the sapphire substrate by using a similar etchant, the GaN semiconductor layer at the bottom of the via hole is removed by RIE to expose a Au pad electrically connected to the source of GaN FET. Thereafter, a thick Au film electrically connected to the Au pad is made through the via hole.Type: GrantFiled: May 21, 1999Date of Patent: May 29, 2001Assignee: Sony CorporationInventor: Hiroji Kawai
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Patent number: 6235617Abstract: It is intended to provide a semiconductor device and its manufacturing method in which a high-resistance region maintaining a high resistance even under high temperatures can be made in a nitride III-V compound semiconductor layer having an electric conductivity by ion implantation. After a nitride III-V compound semiconductor layer having an electric conductivity is grown, a high resistance region is formed in the nitride III-V compound semiconductor layer by locally implanting boron ions therein. The amount of implanted boron is preferably not less than {fraction (1/30)}, or more preferably not less than {fraction (1/15)}, of the carrier concentration of the nitride III-V compound semiconductor layer. The high-resistance region is used as a device isolating region of an electron moving device or as a current blocking layer of a semiconductor laser.Type: GrantFiled: June 6, 2000Date of Patent: May 22, 2001Assignee: Sony CorporationInventor: Hiroji Kawai
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Patent number: 6140169Abstract: A GaN-type field effect transistor exhibits a large input amplitude by using a gate insulating film. A channel layer and a gate insulating film are sequentially laminated on a substrate with a buffer layer therebetween. A gate electrode is formed on the gate insulating film. A source electrode and a drain electrode are disposed at the both sides of the gate electrode and are electrically connected to the channel layer via openings. The channel layer is formed from n-type GaN. The gate insulating film is made from AlN, which exhibits excellent insulation characteristics, thus increasing the Schottky barrier and achieving a large input amplitude. If the FET is operated in the enhancement mode, it is operable in a manner similar to a Si-MOS-type FET, resulting in the formation of an inversion layer.Type: GrantFiled: April 1, 1999Date of Patent: October 31, 2000Assignee: Sony CorporationInventors: Hiroji Kawai, Shunji Imanaga
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Patent number: 6121636Abstract: A semiconductor light emitting device is provided, which does not deteriorate in luminance, maintains a high reliability, permits more free choice of an adhesive, and promises effective extraction of light to the exterior even when it is bonded to a lead frame or other support with the adhesive in practical use. In a GaN light emitting diode, GaN compound semiconductor layers are stacked sequentially on a front surface of a sapphire substrate to form a light emitting diode structure, and a reflective film is formed on a rear surface. Alternatively, the GaN compound semiconductor layers forming the light emitting diode structure are selectively removed by etching to define an inverted mesa-shaped end surface, and the reflective film is formed on the end surface. Both the p-side electrode and the n-side electrode are formed on a common side of the substrate where the GaN compound semiconductor layers are formed.Type: GrantFiled: May 5, 1998Date of Patent: September 19, 2000Assignees: Sony Corporation, Sony Chemicals CorporationInventors: Etsuo Morita, Hiroji Kawai
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Patent number: 6111273Abstract: It is intended to provide a semiconductor device and its manufacturing method in which a high-resistance region maintaining a high resistance even under high temperatures can be made in a nitride III-V compound semiconductor layer having an electric conductivity by ion implantation. After a nitride III-V compound semiconductor layer having an electric conductivity is grown, a high resistance region is formed in the nitride III-V compound semiconductor layer by locally implanting boron ions therein. The amount of implanted boron is preferably not less than 1/30, or more preferably not less than 1/15, of the carrier concentration of the nitride III-V compound semiconductor layer. The high-resistance region is used as a device isolating region of an electron moving device or as a current blocking layer of a semiconductor laser.Type: GrantFiled: January 21, 1999Date of Patent: August 29, 2000Assignee: Sony CorporationInventor: Hiroji Kawai
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Patent number: 6107162Abstract: A semiconductor device such as a semiconductor layer is formed of a compound semiconductor layer of III-V group such as GaN. In the case where the substrate has not any planes that are easy to cleave which coincides with an easy-to-cleave plane of a semiconductor layer grown on the substrate or the substrate easily succumbs to cleavage, then the semiconductor layer together with the substrate can be broken into chips in an easy-to-cleave plane. The cleaved surface of the semiconductor layer can be positively formed as an optically superior surface. A compound semiconductor layer 2 containing at least one of the elements {Ga, Al, In} and N is formed on the substrate 1. This compound semiconductor layer 2 has a pair of facets of {11-20} plane substantially perpendicular to the substrate 1.Type: GrantFiled: April 14, 1998Date of Patent: August 22, 2000Assignee: Sony CorporationInventors: Etsuo Morita, Hiroji Kawai
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Patent number: 6081001Abstract: A luminous intensity of a semiconductor light emitting device having a multi-layer structure formed of nitride group III-V compound semiconductors is improved by having a thickness d of a light emitting layer (active layer) of the semiconductor light emitting device having a multi-layer structure formed of nitride group III-V compound semiconductors ranging from 0.3 nm to 1.5 nm.Type: GrantFiled: March 12, 1997Date of Patent: June 27, 2000Assignee: Sony CorporationInventors: Kenji Funato, Tsunenori Asatsuma, Hiroji Kawai
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Patent number: 6064082Abstract: A heterojunction field effect transistor realizing a high performance by a significant decrease. in source resistance while maintaining a sufficiently high gate resistivity to voltage is provided. Sequentially stacked on a c-face sapphire substrate via a buffer layer are an undoped GaN layer, undoped Al.sub.0.3 Ga.sub.07 N layer, undoped GaN channel layer, undoped Al.sub.0.15 Ga.sub.0.85 N spacer layer, n-type Al.sub.0.15 Ga.sub.0.85 N electron supply layer, graded undoped Al.sub.z Ga.sub.1-z N barrier layer and n-type Al.sub.0.06 Ga.sub.0.94 N contact layer, and a gate electrode, source electrode and drain electrode are formed on the n-type Al.sub.0.06 Ga.sub.0.94 N contact layer to form a AlGaN/GaN HEMT. The Al composition z in the graded undoped Al.sub.z Ga.sub.1-z N barrier layer continuously decreases from 0.15 to 0.06, for example, from the n-type Al.sub.0.15 Ga.sub.0.85 N electron supply layer toward the n-type Al.sub.0.06 Ga.sub.0.94 N contact layer. An n.sup.Type: GrantFiled: May 29, 1998Date of Patent: May 16, 2000Assignee: Sony CorporationInventors: Hiroji Kawai, Shunji Imanaga, Toshimasa Kobayashi
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Patent number: 6043140Abstract: A new and improved method for growing a p-type nitride III-V compound semiconductor is provided which can produce a p-type nitride compound semiconductors having a high carrier concentration, without the need for annealing to activate impurities after growth. In a preferred embodiment, a p-type nitride compound semiconductor, such as p-type GaN, is grown by metal organic chemical vapor deposition methods using a nitrogen source material which does not release hydrogen during release of nitrogen and the semiconductor is grown in an inactive gas. The nitrogen source materials may be selected from nitrogen compounds that contain hydrogen radicals and alkyl radicals and/or phenyl radicals provided that the total amount of hydrogen radicals is less than or equal to the sum total of alkyl radicals and phenyl radicals present in the nitrogen compound used as the nitrogen source material.Type: GrantFiled: June 3, 1997Date of Patent: March 28, 2000Assignee: Sony CorporationInventors: Hiroji Kawai, Tsunenori Asatsuma, Fumihiko Nakamura
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Patent number: 5981980Abstract: To provide a semiconductor laminating structure in which an epitaxial growth of a GaN system material is achieved on a substrate with an excellent matching property with the substrate. The semiconductor laminating structure includes the substrate having a perovskite structure and at least one GaN system chemical compound semiconductor layer formed on the substrate, wherein a major surface of the substrate is formed of a (111) crystal surface.Type: GrantFiled: April 18, 1997Date of Patent: November 9, 1999Assignee: Sony CorporationInventors: Takao Miyajima, Yann Le Bellego, Hiroji Kawai
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Patent number: 5929467Abstract: A GaN-type field effect transistor exhibits a large input amplitude by using a gate insulating film. A channel layer and a gate insulating film are sequentially laminated on a substrate with a buffer layer therebetween. A gate electrode is formed on the gate insulating film. A source electrode and a drain electrode are disposed at the both sides of the gate electrode and are electrically connected to the channel layer via openings. The channel layer is formed from n-type GaN. The gate insulating film is made from AlN, which exhibits excellent insulation characteristics, thus increasing the Schottky barrier and achieving a large input amplitude. If the FET is operated in the enhancement mode, it is operable in a manner similar to a Si-MOS-type FET, resulting in the formation of an inversion layer.Type: GrantFiled: December 3, 1997Date of Patent: July 27, 1999Assignee: Sony CorporationInventors: Hiroji Kawai, Shunji Imanaga
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Patent number: 5863811Abstract: A method for growing a single crystal III-V compound semiconductor layer, in which grown by vapor deposition on a first single crystal III-V compound semiconductor layer including at least Ga and N is a second single crystal III-V compound semiconductor layer different from the first layer and including at least Ga and N, comprises the steps of: growing a buffer layer other than single crystal and having substantially the same composition as that of the second layer by vapor deposition on the first layer; and growing the second layer on the buffer layer. A method for growing a single crystal AlGaN layer on a single crystal GaN layer by vapor deposition, comprises the steps of: growing a buffer layer of a III-V compound semiconductor including at least Ga and N on the single crystal GaN layer by vapor deposition; and growing the single crystal AlGaN layer on the buffer layer by vapor deposition.Type: GrantFiled: June 26, 1996Date of Patent: January 26, 1999Assignee: Sony CorporationInventors: Hiroji Kawai, Tsunenori Asatsuma, Kenji Funato