Patents by Inventor Hiroji Ozaki

Hiroji Ozaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4998161
    Abstract: In an element forming region (10) of a semiconductor substrate (1), there are provided a gate electrode (2), sidewall insulating films (4), impurity diffusion regions (5a and 5b) of a lower concentration having their one ends are overlapped with the side sections of the gate electrode (2), and impurity diffusion regions (6a and 6b) of a higher concentration having their one ends are overlapped with the side sections of the sidewall insulating films (4). In an element isolation region (7) of the semiconductor substrate, there are formed an electrostatic screening electrode (31) for element isolation and an insulating film (30) substantially enclosing the electrostatic screening electrode. By employing the electrostatic screening electrode (31) for element isolation in the LDD MOS transistor, there is obtained a semiconductor device of high performance and reliability which is free from intrusion of impurities from the element isolation region.
    Type: Grant
    Filed: December 5, 1989
    Date of Patent: March 5, 1991
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hiroshi Kimura, Shinichi Satoh, Hiroji Ozaki, Yoshinori Tanaka, Wataru Wakamiya
  • Patent number: 4996168
    Abstract: An improved method for manufacturing P type semiconductor device such as used for memories is disclosed. Channeling such as caused by an ion implantation process is prevented by adopting a diffusion method to diffuse boron (7) from a boron glass formed on a layer of polysilicon or silicon oxide on a semiconductor substrate. This method provides a semiconductor device with shallow P type impurity diffusion regions.
    Type: Grant
    Filed: November 1, 1988
    Date of Patent: February 26, 1991
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hiroji Ozaki, Shigeo Nagao
  • Patent number: 4994893
    Abstract: A semiconductor device has MOS field effect transistors isolated by a field shield. The field shield has a gate of conductor layers formed spaced apart from each other on a silicon substrate through an insulating film and with the surface thereof being covered with an insulating film. In regions isolated by the field shield, MOS field effect transistors are formed. Each of the MOS field effect transistors has a gate electrode of a conductor layer formed on the silicon substrate through an insulating film and with the surface thereof being covered with an insulating film. An impurity diffused region is formed in a region on the silicon substrate between the gate electrode and the field shield. A portion on an exposed surface of the impurity diffused region between the field shield and the gate electrode is selectively filled with a tungsten buried layer. The tungsten buried layer is formed, flattened relative to the gate electrode and the gate constituting the field shield.
    Type: Grant
    Filed: September 11, 1989
    Date of Patent: February 19, 1991
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hiroji Ozaki, Takahisa Eimori, Yoshinori Tanaka, Wataru Wakamiya, Shinichi Satoh
  • Patent number: 4984055
    Abstract: A semiconductor device having a plurality of conductive layers is disclosed. The device has first level conductors (9) formed spaced apart on a semiconductor substrate (1). The semiconductor substrate (1) is provided with impurity diffusion regions (11) in its major surface between adjacent first level conductors (9). A triple layer insulation formed of a pair of oxide layers (12, 14) and an silicon oxide layer (13) sandwiched between the oxide layers (12, 14) covers the semiconductor substrate (1) and the first level conductors (9) thereon. At least one contact hole (15) is formed to extend through the triple layer insulation to either the impurity diffusion region (11) in the semiconductor substrate (1) or the first level conductor (9) on the semiconductor substrate (1). A second level conductor (16, 17) is provided on the triple layer insulation and on the inner surrounding wall of the contact hole (15).
    Type: Grant
    Filed: November 7, 1988
    Date of Patent: January 8, 1991
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yoshinori Okumura, Atsuhiro Fujii, Masao Nagatomo, Hiroji Ozaki, Wataru Wakamiya, Takayuki Matsukawa
  • Patent number: 4956310
    Abstract: A semiconductor memory device in accordance with the present invention comprises: a semiconductor substrate (1) of a first conductivity type; a charge storage region (6) and a bit line region (7) of a second conductivity type formed on a main surface of the substrate; highly doped regions (12a, 12b) of the first conductivity type formed respectively contiguous to only the bottom boundaries of the charge storage region (6) and the bit line region (7).
    Type: Grant
    Filed: October 5, 1988
    Date of Patent: September 11, 1990
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Akira Tokui, Shinichi Sato, Akira Kawai, Masayuki Nakajima, Hiroji Ozaki, Masao Nagatomo
  • Patent number: 4956692
    Abstract: Two trenches are formed at a predetermined distance on a main surface of a semiconductor substrate. An oxide film and a nitride film are successively formed on the main surface of the semiconductor including the inner surfaces of the trenches. After a resist is formed over the whole surface including the inner surfaces of the trenches, the resist is patterned to expose a portion of the nitride film on a side surface of each trench. The exposed portions of the nitride film are removed by using the patterned resist as a mask and thermal oxidation is applied. Then, an isolation oxide film is formed on a region between the trenches and an end of a bird's beak is located on a side surface of each trench and is connected to the oxide film formed in each trench.
    Type: Grant
    Filed: November 3, 1988
    Date of Patent: September 11, 1990
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hiroji Ozaki, Masahiro Yoneda, Ikuo Ogoh, Yoshinori Okumura, Wataru Wakamiya, Masao Nagatomo
  • Patent number: 4763182
    Abstract: A semiconductor memory device comprises a first conductivity type semiconductor substrate (1) formed thereon with a charge storage region (5) and a second conductivity type region (6) serving as a bit line, and first conductivity type highly concentrated regions (8, 11) higher in concentration than the semiconductor substrate (1) at least by one digit are formed to enclose the charge storage region (5) and the bit line region (6) respectively. Thus, potential barriers against electrons can be defined in interfaces between the highly concentrated region (8) and the charge storage region (5) and between the highly concentrated region (11) and the bit line region (6), thereby to prevent malfunction caused by incidence of radioactive rays such as alpha rays.
    Type: Grant
    Filed: December 12, 1986
    Date of Patent: August 9, 1988
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hiroji Ozaki, Shinichi Sato, Akira Tokui, Akira Kawai, Masayuki Nakajima, Masao Nagatomo
  • Patent number: 4702796
    Abstract: The present invention is a method for fabricating a semiconductor device, wherein impurity is selectively diffused to surround a region (7) of a second conductivity type as a bit line formed on a semiconductor substrate (1), thereby forming an impurity diffused region (9) of a first conductivity type having high density and, by extending the impurity diffused region (9) in the element separating step to form a high density region of the first conductivity type having high density.
    Type: Grant
    Filed: November 14, 1986
    Date of Patent: October 27, 1987
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Masayuki Nakajima, Shinichi Sato, Akira Tokui, Akira Kawai, Masao Nagatomo, Hiroji Ozaki