Patents by Inventor Hirokazu Ejiri

Hirokazu Ejiri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240096915
    Abstract: A solid-state image pickup apparatus according to a first aspect of the present technology includes a photoelectric conversion section that generates and holds a charge in response to incident light, a transfer section that includes a V-NW transistor (Vertical Nano Wire transistor) and transfers the charge held in the photoelectric conversion section, and an accumulation section that includes a wiring layer connected to a drain of the transfer section including the V-NW transistor and accumulates the charge transferred by the transfer section. The present technology is applicable to a CMOS image sensor, for example.
    Type: Application
    Filed: September 28, 2023
    Publication date: March 21, 2024
    Inventors: HIROAKI AMMO, HIROKAZU EJIRI, AKIKO HONJO
  • Patent number: 11804500
    Abstract: A solid-state image pickup apparatus according to a first aspect of the present technology includes a photoelectric conversion section that generates and holds a charge in response to incident light, a transfer section that includes a V-NW transistor (Vertical Nano Wire transistor) and transfers the charge held in the photoelectric conversion section, and an accumulation section that includes a wiring layer connected to a drain of the transfer section including the V-NW transistor and accumulates the charge transferred by the transfer section. The present technology is applicable to a CMOS image sensor, for example.
    Type: Grant
    Filed: July 7, 2021
    Date of Patent: October 31, 2023
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Hiroaki Ammo, Hirokazu Ejiri, Akiko Honjo
  • Publication number: 20230275112
    Abstract: To provide a semiconductor device with which it is possible to reduce parasitic capacitance between electrodes for a resistance element, and a method for manufacturing the semiconductor device. A semiconductor device according to the present disclosure includes: a substrate; a first resistance layer provided on the substrate; a first electrode in contact with a lower surface of the first resistance layer; and a second electrode in contact with an upper surface of the first resistance layer.
    Type: Application
    Filed: April 6, 2021
    Publication date: August 31, 2023
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Hirokazu EJIRI, Jun OGI, Yuki KAWAHARA, Chigusa YAMANE
  • Publication number: 20220077207
    Abstract: A solid-state imaging device according to an embodiment of the present disclosure includes a mode-switching switch section that, in a first mode, electrically couples a first signal path to a photoelectric conversion section and electrically decouples a second signal path from the photoelectric conversion section, and that, in a second mode, electrically couples both of the first signal path and the second signal path to the photoelectric conversion section. At least the photoelectric conversion section is formed in a first substrate, and at least a second amplification transistor is formed in a second substrate, among the first substrate and the second substrate stacked on each other.
    Type: Application
    Filed: October 29, 2019
    Publication date: March 10, 2022
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Hirokazu EJIRI
  • Publication number: 20220021826
    Abstract: An imaging device includes a first substrate including at least one sensor portion that converts light into electric charge, and a second substrate including a first portion of a readout circuit having at least one first transistor. The readout circuit outputs a pixel signal based on the electric charge. The imaging device includes a third substrate including a logic circuit that performs processing on the pixel signal. The first substrate, the second substrate, and the third substrate are stacked in that order.
    Type: Application
    Filed: December 9, 2019
    Publication date: January 20, 2022
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Hirokazu EJIRI
  • Publication number: 20210343767
    Abstract: A solid-state image pickup apparatus according to a first aspect of the present technology includes a photoelectric conversion section that generates and holds a charge in response to incident light, a transfer section that includes a V-NW transistor (Vertical Nano Wire transistor) and transfers the charge held in the photoelectric conversion section, and an accumulation section that includes a wiring layer connected to a drain of the transfer section including the V-NW transistor and accumulates the charge transferred by the transfer section. The present technology is applicable to a CMOS image sensor, for example.
    Type: Application
    Filed: July 7, 2021
    Publication date: November 4, 2021
    Inventors: HIROAKI AMMO, HIROKAZU EJIRI, AKIKO HONJO
  • Patent number: 11121158
    Abstract: The present technology relates to a solid-state image pickup apparatus and electronic equipment that makes it possible to suppress read noise. A solid-state image pickup apparatus according to a first aspect of the present technology includes a photoelectric conversion section that generates and holds a charge in response to incident light, a transfer section that includes a V-NW transistor (Vertical Nano Wire transistor) and transfers the charge held in the photoelectric conversion section, and an accumulation section that includes a wiring layer connected to a drain of the transfer section including the V-NW transistor and accumulates the charge transferred by the transfer section. The present technology is applicable to a CMOS image sensor, for example.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: September 14, 2021
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Hiroaki Ammo, Hirokazu Ejiri, Akiko Honjo
  • Patent number: 11069801
    Abstract: A semiconductor device, an electronic apparatus, and a method of manufacturing a semiconductor device with reduced RTN influence regardless of gate electrode shape are disclosed. In one example, a semiconductor device includes a substrate having an element region and an element separating region, the element region including a source region and a drain region, and a channel region between the source and drain regions. The element separating region is arranged on both sides in a direction orthogonal to the source, channel and drain region arrangement direction. A gate insulating film is provided on the element region of the substrate from one side to another side of the element separating region. A gate electrode is provided on the gate insulating film, and includes an impurity having a different concentration in a boundary region as compared to a central region.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: July 20, 2021
    Assignee: Sony Semiconductor Solutions Corporation
    Inventor: Hirokazu Ejiri
  • Patent number: 10841521
    Abstract: The present disclosure relates to an information processing device, an information processing method, and a program that enable generation of stable PUFs. The information processing device includes: a reading unit that reads output data from a predetermined element a plurality of times; an average value calculation unit that calculates average values of the output data read by the reading unit; a median calculation unit that calculates the median of the average values calculated by the average value calculation unit; and a PUF generation unit that generates a physical unclonable function (PUF) by comparing the median with the average values. The predetermined element is an image sensor, and the reading unit reads output data from the image sensor when the image sensor is shielded from light. The present technology can be applied to imaging devices, for example.
    Type: Grant
    Filed: December 8, 2016
    Date of Patent: November 17, 2020
    Assignee: Sony Corporation
    Inventors: Koichi Baba, Taiichiro Watanabe, Hirokazu Ejiri
  • Publication number: 20200267341
    Abstract: The present disclosure relates to an information processing device, an information processing method, and a program that enable generation of stable PUFs. The information processing device includes: a reading unit that reads output data from a predetermined element a plurality of times; an average value calculation unit that calculates average values of the output data read by the reading unit; a median calculation unit that calculates the median of the average values calculated by the average value calculation unit; and a PUF generation unit that generates a physical unclonable function (PUF) by comparing the median with the average values. The predetermined element is an image sensor, and the reading unit reads output data from the image sensor when the image sensor is shielded from light. The present technology can be applied to imaging devices, for example.
    Type: Application
    Filed: December 8, 2016
    Publication date: August 20, 2020
    Applicant: SONY CORPORATION
    Inventors: Koichi BABA, Taiichiro WATANABE, Hirokazu EJIRI
  • Publication number: 20200194582
    Abstract: A semiconductor device, an electronic apparatus, and a method of manufacturing a semiconductor device with reduced RTN influence regardless of gate electrode shape are disclosed. In one example, a semiconductor device includes a substrate having an element region and an element separating region, the element region including a source region and a drain region, and a channel region between the source and drain regions. The element separating region is arranged on both sides in a direction orthogonal to the source, channel and drain region arrangement direction. A gate insulating film is provided on the element region of the substrate from one side to another side of the element separating region. A gate electrode is provided on the gate insulating film, and includes an impurity having a different concentration in a boundary region as compared to a central region.
    Type: Application
    Filed: July 26, 2018
    Publication date: June 18, 2020
    Inventor: Hirokazu Ejiri
  • Publication number: 20200020728
    Abstract: The present technology relates to a solid-state image pickup apparatus and electronic equipment that makes it possible to suppress read noise. A solid-state image pickup apparatus according to a first aspect of the present technology includes a photoelectric conversion section that generates and holds a charge in response to incident light, a transfer section that includes a V-NW transistor (Vertical Nano Wire transistor) and transfers the charge held in the photoelectric conversion section, and an accumulation section that includes a wiring layer connected to a drain of the transfer section including the V-NW transistor and accumulates the charge transferred by the transfer section. The present technology is applicable to a CMOS image sensor, for example.
    Type: Application
    Filed: March 16, 2018
    Publication date: January 16, 2020
    Inventors: HIROAKI AMMO, HIROKAZU EJIRI, AKIKO HONJO
  • Patent number: 9368539
    Abstract: Disclosed is a semiconductor device including a first semiconductor substrate and a first atom diffusion prevention portion, the first atom diffusion prevention portion being arranged at a part on the first semiconductor substrate and configured to prevent diffusion of an atom having a dangling bond terminating effect.
    Type: Grant
    Filed: February 24, 2015
    Date of Patent: June 14, 2016
    Assignee: Sony Corporation
    Inventors: Koichi Baba, Masaaki Bairo, Hirokazu Ejiri
  • Publication number: 20150249107
    Abstract: Disclosed is a semiconductor device including a first semiconductor substrate and a first atom diffusion prevention portion, the first atom diffusion prevention portion being arranged at a part on the first semiconductor substrate and configured to prevent diffusion of an atom having a dangling bond terminating effect.
    Type: Application
    Filed: February 24, 2015
    Publication date: September 3, 2015
    Inventors: Koichi Baba, Masaaki Bairo, Hirokazu Ejiri
  • Patent number: 7781861
    Abstract: By stably separating a melting location of a fuse (3) from conductive layers (5A, 5B), reliable melting of the fuse (3) is enabled. A fuse (3) including a fuse body (3A) and two pads (3Ba, 3Bb) connected by this and two conductive layers (5A, 5B) individually connected to the two pads (3Ba, 3Bb) are formed in a multilayer structure on a semiconductor substrate (1). A length of the fuse body (3A) is defined so that the melting location of the fuse (3) becomes positioned in the fuse body (3A) away from the region overlapped on the conductive layer (5A or 5B) when an electrical stress is applied between two conductive layers (5A, 5B) and the fuse (3) is melted.
    Type: Grant
    Filed: March 30, 2004
    Date of Patent: August 24, 2010
    Assignee: Sony Corporation
    Inventors: Hideki Mori, Hirokazu Ejiri, Kenji Azami, Terukazu Ohno, Nobuyuki Yoshitake
  • Patent number: 7192826
    Abstract: Disclosed is a semiconductor device in which the capacitive element of MIMC structure has a low parasitic capacity. A process for fabrication of said semiconductor device. The semiconductor device has a capacitive element of MIMC structure, a PN photodiode, and a vertical NPN bipolar transistor which are mounted together on the same semiconductor substrate. The lower wiring layer connected to the TiN lower electrode layer of the capacitive element of MIMC structure is formed on the insulating film and the first interlayer insulating film. Between this insulating film and the p-type semiconductor substrate is the p?-type low-concentration semiconductor layer whose impurity concentration is lower than that of the p-type semiconductor substrate. This construction suppresses the parasitic capacity of the capacitive element of the MIMC structure.
    Type: Grant
    Filed: August 4, 2004
    Date of Patent: March 20, 2007
    Assignee: Sony Corporation
    Inventors: Hirokazu Ejiri, Shigeru Kanematsu
  • Publication number: 20060263986
    Abstract: By stably separating a melting location of a fuse (3) from conductive layers (5A, 5B), reliable melting of the fuse (3) is enabled. A fuse (3) including a fuse body (3A) and two pads (3Ba, 3Bb) connected by this and two conductive layers (5A, 5B) individually connected to the two pads (3Ba, 3Bb) are formed in a multilayer structure on a semiconductor substrate (1). A length of the fuse body (3A) is defined so that the melting location of the fuse (3) becomes positioned in the fuse body (3A) away from the region overlapped on the conductive layer (5A or 5B) when an electrical stress is applied between two conductive layers (5A, 5B) and the fuse (3) is melted.
    Type: Application
    Filed: March 30, 2004
    Publication date: November 23, 2006
    Applicant: Sony Corporation
    Inventors: Hideki Mori, Hirokazu Ejiri, Kenji Azami, Terukazu Ohno, Nobuyuki Yoshitake
  • Patent number: 7101750
    Abstract: A semiconductor device for an integrated injection logic cell having a pnp bipolar transistor structure formed on a semiconductor substrate, wherein at least one layer of insulating films formed on a base region of the pnp bipolar transistor structure is comprised of a silicon nitride film. The semiconductor device of the present invention is advantageous in that the silicon nitride film constituting at least one layer of the insulating films formed on the base region of the pnp bipolar transistor prevents an occurrence of contamination on the surface of the base region, so that both the properties of the pnp bipolar transistor and the operation of the IIL cell can be stabilized. Further, by the process of the present invention, the above-mentioned excellent semiconductor device can be produced.
    Type: Grant
    Filed: September 27, 2004
    Date of Patent: September 5, 2006
    Assignee: Sony Corporation
    Inventor: Hirokazu Ejiri
  • Publication number: 20050179060
    Abstract: A semiconductor device for an integrated injection logic cell having a pnp bipolar transistor structure formed on a semiconductor substrate, wherein at least one layer of insulating films formed on a base region of the pnp bipolar transistor structure is comprised of a silicon nitride film. The semiconductor device of the present invention is advantageous in that the silicon nitride film constituting at least one layer of the insulating films formed on the base region of the pnp bipolar transistor prevents an occurrence of contamination on the surface of the base region, so that both the properties of the pnp bipolar transistor and the operation of the IIL cell can be stabilized. Further, by the process of the present invention, the above-mentioned excellent semiconductor device can be produced.
    Type: Application
    Filed: April 11, 2005
    Publication date: August 18, 2005
    Inventor: Hirokazu Ejiri
  • Patent number: 6919615
    Abstract: A semiconductor device for an integrated injection logic cell having a pnp bipolar transistor structure formed on a semiconductor substrate, wherein at least one layer of insulating films formed on a base region of the pnp bipolar transistor structure is comprised of a silicon nitride film. The semiconductor device of the present invention is advantageous in that the silicon nitride film constituting at least one layer of the insulating films formed on the base region of the pnp bipolar transistor prevents an occurrence of contamination on the surface of the base region, so that both the properties of the pnp bipolar transistor and the operation of the IIL cell can be stabilized. Further, by the process of the present invention, the above-mentioned excellent semiconductor device can be produced.
    Type: Grant
    Filed: January 14, 2003
    Date of Patent: July 19, 2005
    Assignee: Sony Corporation
    Inventor: Hirokazu Ejiri