Abstract: A semiconductor device for an integrated injection logic cell having a pnp bipolar transistor structure formed on a semiconductor substrate, wherein at least one layer of insulating films formed on a base region of the pnp bipolar transistor structure is comprised of a silicon nitride film. The semiconductor device of the present invention is advantageous in that the silicon nitride film constituting at least one layer of the insulating films formed on the base region of the pnp bipolar transistor prevents an occurrence of contamination on the surface of the base region, so that both the properties of the pnp bipolar transistor and the operation of the IIL cell can be stabilized. Further, by the process of the present invention, the above-mentioned excellent semiconductor device can be produced.

Abstract: Disclosed is a semiconductor device in which the capacitive element of MIMC structure has a low parasitic capacity. A process for fabrication of said semiconductor device. The semiconductor device has a capacitive element of MIMC structure, a PN photodiode, and a vertical NPN bipolar transistor which are mounted together on the same semiconductor substrate. The lower wiring layer connected to the TiN lower electrode layer of the capacitive element of MIMC structure is formed on the insulating film and the first interlayer insulating film. Between this insulating film and the p-type semiconductor substrate is the p?-type low-concentration semiconductor layer whose impurity concentration is lower than that of the p-type semiconductor substrate. This construction suppresses the parasitic capacity of the capacitive element of the MIMC structure.

Abstract: Disclosed is a method for production of a semiconductor device having capacitive elements. The method includes steps of covering an insulating film formed on a substrate sequentially with a lower electrode film, a dielectric film, and an upper electrode film; applying a photoresist to the top of the films in laminate structure by photolithography, thereby forming a photoresist pattern to form an upper electrode; performing selective etching on the upper electrode film by using the photoresist pattern to form the upper electrode as a mask, thereby forming the upper electrode pattern; covering the upper electrode pattern with a photoresist pattern to form a dielectric pattern; and performing selective etching on the dielectric film by using the photoresist pattern to form the dielectric as a mask, thereby forming the dielectric pattern. The above-mentioned production method prevents a short circuit between the upper electrode and the lower electrode when the capacitive element is formed.

Abstract: Disclosed is a semiconductor device in which the capacitive element of MIMC structure has a low parasitic capacity. A process for fabrication of said semiconductor device. The semiconductor device has a capacitive element of MIMC structure, a PN photodiode, and a vertical NPN bipolar transistor which are mounted together on the same semiconductor substrate. The lower wiring layer connected to the TiN lower electrode layer of the capacitive element of MIMC structure is formed on the insulating film and the first interlayer insulating film. Between this insulating film and the p-type semiconductor substrate is the p−-type low-concentration semiconductor layer whose impurity concentration is lower than that of the p-type semiconductor substrate. This construction suppresses the parasitic capacity of the capacitive element of the MIMC structure.

Abstract: The present invention relates to a semiconductor device in which a capacitance element is mounted on a semiconductor substrate as well as a method of fabricating the device. According to the present invention, a substantial lower electrode is formed on a semiconductor substrate through a first insulation film; a peripheral electrode, i.e. the periphery of the lower electrode or a dummy electrode, which has the surface higher than the surface of the lower electrode being formed integrally with or separately from the lower electrode; an upper electrode being formed on the lower electrode through a dielectric film; a capacitance element being formed so that at least the surface of the dielectric film may lie on a level lower than the surface of the peripheral electrode; and a recess surrounded by the peripheral electrode being filled with a smoothing film.

Abstract: In order to prevent a capacitance element from suffering fluctuation in the capacitance value and deterioration of the reliability caused in the step for planarizing the surface of the substrate after forming the capacitance element, there is provided a process for fabricating a semiconductor device, in which an insulator is formed on a semiconductor substrate; a first wiring layer to be a lower portion electrode; a Ta2O5 layer to be a dielectric film; a second wiring layer to be an upper portion electrode are successively formed; a pattern for the dielectric film and upper portion electrode is formed; a pattern for the lower portion electrode is subsequently formed; an SiN film is formed as a protective film; and planarization is conducted by etching back a spin on glass (SOG).

Abstract: A semiconductor device for an integrated injection logic cell having a pnp bipolar transistor structure formed on a semiconductor substrate, wherein at least one layer of insulating films formed on a base region of the pnp bipolar transistor structure is comprised of a silicon nitride film. The semiconductor device of the present invention is advantageous in that the silicon nitride film constituting at least one layer of the insulating films formed on the base region of the pnp bipolar transistor prevents an occurrence of contamination on the surface of the base region, so that both the properties of the pnp bipolar transistor and the operation of the IIL cell can be stabilized. Further, by the process of the present invention, the above-mentioned excellent semiconductor device can be produced.

Abstract: A semiconductor device for an integrated injection logic cell having a pnp bipolar transistor structure formed on a semiconductor substrate, wherein at least one layer of insulating films formed on a base region of the pnp bipolar transistor structure is comprised of a silicon nitride film. The semiconductor device of the present invention is advantageous in that the silicon nitride film constituting at least one layer of the insulating films formed on the base region of the pnp bipolar transistor prevents an occurrence of contamination on the surface of the base region, so that both the properties of the pnp bipolar transistor and the operation of the IIL cell can be stabilized. Further, by the process of the present invention, the above-mentioned excellent semiconductor device can be produced.

Abstract: The present invention relates to a semiconductor device in which a capacitance element is mounted on a semiconductor substrate as well as a method of fabricating the device. According to the present invention, a substantial lower electrode is formed on a semiconductor substrate through a first insulation film; a peripheral electrode, i.e. the periphery of the lower electrode or a dummy electrode, which has the surface higher than the surface of the lower electrode being formed integrally with or separately from the lower electrode; an upper electrode being formed on the lower electrode through a dielectric film; a capacitance element being formed so that at least the surface of the dielectric film may lie on a level lower than the surface of the peripheral electrode; and a recess surrounded by the peripheral electrode being filled with a smoothing film.

Abstract: Disclosed is a semiconductor device in which the capacitive element of MIMC structure has a low parasitic capacity. A process for fabrication of said semiconductor device. The semiconductor device has a capacitive element of MIMC structure, a PN photodiode, and a vertical NPN bipolar transistor which are mounted together on the same semiconductor substrate. The lower wiring layer connected to the TiN lower electrode layer of the capacitive element of MIMC structure is formed on the insulating film and the first interlayer insulating film. Between this insulating film and the p-type semiconductor substrate is the p−-type low-concentration semiconductor layer whose impurity concentration is lower than that of the p-type semiconductor substrate. This construction suppresses the parasitic capacity of the capacitive element of the MIMC structure.

Abstract: In order to prevent a capacitance element from suffering fluctuation in the capacitance value and deterioration of the reliability caused in the step for planarizing the surface of the substrate after forming the capacitance element, there is provided a process for fabricating a semiconductor device, in which an insulator is formed on a semiconductor substrate; a first wiring layer to be a lower portion electrode; a Ta2O5 layer to be a dielectric film; a second wiring layer to be an upper portion electrode are successively formed; a pattern for the dielectric film and upper portion electrode is formed; a pattern for the lower portion electrode is subsequently formed; an SiN film is formed as a protective film; and planarization is conducted by etching back a spin on glass (SOG).

Abstract: A semiconductor device for an integrated injection logic cell having a pnp bipolar transistor structure formed on a semiconductor substrate, wherein at least one layer of insulating films formed on a base region of the pnp bipolar transistor structure is comprised of a silicon nitride film. The semiconductor device of the present invention is advantageous in that the silicon nitride film constituting at least one layer of the insulating films formed on the base region of the pnp bipolar transistor prevents an occurrence of contamination on the surface of the base region, so that both the properties of the pnp bipolar transistor and the operation of the IIL cell can be stabilized. Further, by the process of the present invention, the above-mentioned excellent semiconductor device can be produced.

Abstract: In a semiconductor device by a complex-type bipolar transistor device in which a junction-type field effect transistor is connected to a bipolar transistor, to make it possible to ensure a good and stable characteristic of the bipolar transistor without incurring a larger area in the junction-type field effect transistor J-FET.

Abstract: A bipolar semiconductor device includes an npn transistor using a base outlet electrode in the form of a polycrystalline Si film and one or more other devices using an electrode in the form of a polycrystalline Si film supported on a common p-type Si substrate, the sheet resistance of the polycrystalline Si film forming the base outlet electrode of the npn transistor is decreased to two thirds of the sheet resistance of the polycrystalline Si film forming at least one electrode of at least one other device. The base outlet electrode can be made by first making the polycrystalline Si film on the entire surface of the substrate, then applying selective ion implantation of Si to a selective portion of the polycrystalline Si film for making the base outlet electrode to change it into an amorphous state, and then annealing the product to grow the polycrystalline Si film by solid-phase growth.

Abstract: A semiconductor device and a manufacturing method therefor which can simultaneously realize both a reduction in base transit time by a reduction in base width and a reduction in base resistance by a reduction in link base resistance. The semiconductor device is manufactured by the method including the steps of forming a first impurity diffused layer of a first conduction type in a semiconductor substrate; forming a conducting film connected to the first impurity diffused layer; forming a first insulating film on the conducting film; forming a first hole through a laminated film composed of the first insulating film and the conducting film; forming a second impurity diffused layer of the first conduction type in the semiconductor substrate exposed to the first hole; forming a side wall from a second insulating film in the first hole to form a second hole; and forming a third impurity diffused layer of the first conduction type in the semiconductor substrate exposed to the second hole.

Abstract: A semiconductor device and a manufacturing method therefor which can simultaneously realize both a reduction in base transit time by a reduction in base width and a reduction in base resistance by a reduction in link base resistance. The semiconductor device is manufactured by the method including the steps of forming a first impurity diffused layer of a first conduction type in a semiconductor substrate; forming a conducting film connected to the first impurity diffused layer; forming a first insulating film on the conducting film; forming a first hole through a laminated film composed of the first insulating film and the conducting film; forming a second impurity diffused layer of the first conduction type in the semiconductor substrate exposed to the first hole; forming a side wall from a second insulating film in the first hole to form a second hole; and forming a third impurity diffused layer of the first conduction type in the semiconductor substrate exposed to the second hole.

Abstract: A semiconductor device and a manufacturing method therefor which can simultaneously realize both a reduction in base transit time by a reduction in base width and a reduction in base resistance by a reduction in link base resistance. The semiconductor device is manufactured by the method including the steps of forming a first impurity diffused layer of a first conduction type in a semiconductor substrate; forming a conducting film connected to the first impurity diffused layer; forming a first insulating film on the conducting film; forming a first hole through a laminated film composed of the first insulating film and the conducting film; forming a second impurity diffused layer of the first conduction type in the semiconductor substrate exposed to the first hole; forming a side wall from a second insulating film in the first hole to form a second hole; and forming a third impurity diffused layer of the first conduction type in the semiconductor substrate exposed to the second hole.