Patents by Inventor Hirokazu Fujimaki

Hirokazu Fujimaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220406933
    Abstract: A semiconductor structure, the semiconductor structure includes a substrate with a first conductivity type and a laterally diffused metal-oxide-semiconductor (LDMOS) device on the substrate, the LDMOS device includes a first well region on the substrate, and the first well region has a first conductivity type. A second well region with a second conductivity type, the second conductivity type is complementary to the first conductivity type, a source doped region in the second well region with the first conductivity type, and a deep drain doped region in the first well region, the deep drain doped region has the first conductivity type.
    Type: Application
    Filed: September 30, 2021
    Publication date: December 22, 2022
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Hirokazu Fujimaki, Bo-An Tsai, Shih-Ping Lee
  • Patent number: 10734494
    Abstract: A semiconductor device includes insulating substrate; a compound semiconductor layer provided in a first region of a surface of the insulating substrate; and a silicon layer provided in a second region, differing from the first region, of the surface of the insulating substrate. The semiconductor device further includes: a first gate electrode provided on a surface of the compound semiconductor layer; a pair of conductive members provided at positions on the surface of the compound semiconductor layer to sandwich the first gate electrode between the pair of conductive members; a second gate electrode provided on a surface of the silicon layer; and a pair of diffusion layers provided at positions in the silicon layer to sandwich the second gate electrode between the pair of diffusion layers. One of the conductive members is electrically connected to one of the diffusion layers.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: August 4, 2020
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventors: Hirokazu Fujimaki, Koichi Kaneko
  • Patent number: 10497726
    Abstract: A semiconductor device having reduced size, and a manufacturing method of the semiconductor device, where the semiconductor device has a silicon layer provided in a first region on a sapphire substrate, and a silicon device formed on the silicon layer. An oxide semiconductor layer is provided in a second region on the sapphire substrate, and an oxide semiconductor device is formed in the oxide semiconductor layer. The silicon device is connected to the oxide semiconductor device by plural wiring lines formed in a wiring line layer.
    Type: Grant
    Filed: June 15, 2017
    Date of Patent: December 3, 2019
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventors: Hirokazu Fujimaki, Koichi Kaneko
  • Publication number: 20190067432
    Abstract: A semiconductor device includes insulating substrate; a compound semiconductor layer provided in a first region of a surface of the insulating substrate; and a silicon layer provided in a second region, differing from the first region, of the surface of the insulating substrate. The semiconductor device further includes: a first gate electrode provided on a surface of the compound semiconductor layer; a pair of conductive members provided at positions on the surface of the compound semiconductor layer to sandwich the first gate electrode between the pair of conductive members; a second gate electrode provided on a surface of the silicon layer; and a pair of diffusion layers provided at positions in the silicon layer to sandwich the second gate electrode between the pair of diffusion layers. One of the conductive members is electrically connected to one of the diffusion layers.
    Type: Application
    Filed: August 27, 2018
    Publication date: February 28, 2019
    Applicant: LAPIS Semiconductor Co., Ltd.
    Inventors: Hirokazu FUJIMAKI, Koichi KANEKO
  • Publication number: 20170365629
    Abstract: The present disclosure provides a semiconductor device that may reduce the size of the semiconductor device and a manufacturing method thereof. A silicon layer is provided in a first region of on a sapphire substrate, and a silicon device is formed on the silicon layer. An oxide semiconductor layer is provided in a second region on the sapphire substrate, and an oxide semiconductor device is formed in the oxide semiconductor layer. The silicon device is connected to the oxide semiconductor device by plural wiring lines formed in a wiring line layer.
    Type: Application
    Filed: June 15, 2017
    Publication date: December 21, 2017
    Inventors: HIROKAZU FUJIMAKI, KOICHI KANEKO
  • Patent number: 8278198
    Abstract: A method of producing a Schottky diode includes the steps of: forming a resist layer on the semiconductor substrate; performing a first exposure process on the resist layer; performing a first developing process for developing the resist layer to form a first Schottky diode having an excess region; performing a first cleaning process; performing a second exposure process on the first Schottky diode; performing a second developing process on the first Schottky diode to remove the excess region from the first Schottky diode so that a second Schottky diode corresponding to the specific Schottky diode is formed; and performing a second cleaning process.
    Type: Grant
    Filed: August 20, 2010
    Date of Patent: October 2, 2012
    Assignee: Oki Semiconductor Co., Ltd.
    Inventors: Yuuki Doi, Hirokazu Fujimaki
  • Patent number: 7902884
    Abstract: An H-bridge circuit includes a lower-arm field-effect transistor and a current supplying element that turns on when the drain of the lower-arm field-effect transistor is negatively biased due to regenerative current. When turned on, the current supplying element conducts current from the source to the drain of the lower-arm field-effect transistor, in parallel with a parasitic diode inherent in the lower-arm field effect transistor. The current supplying element competes with other parasitic elements that conduct current from peripheral circuitry to the drain of the lower-arm field-effect transistor, thereby reducing the amount of such current drawn through the peripheral circuitry and lessening the impact of the regenerative current on the peripheral circuits.
    Type: Grant
    Filed: September 23, 2009
    Date of Patent: March 8, 2011
    Assignee: Oki Semiconductor Co., Ltd.
    Inventors: Miyuki Kanai, Hirokazu Fujimaki, Takeshi Shimizu
  • Publication number: 20110042775
    Abstract: A method of producing a Schottky diode includes the steps of: forming a resist layer on the semiconductor substrate; performing a first exposure process on the resist layer; performing a first developing process for developing the resist layer to form a first Schottky diode having an excess region; performing a first cleaning process; performing a second exposure process on the first Schottky diode; performing a second developing process on the first Schottky diode to remove the excess region from the first Schottky diode so that a second Schottky diode corresponding to the specific Schottky diode is formed; and performing a second cleaning process.
    Type: Application
    Filed: August 20, 2010
    Publication date: February 24, 2011
    Inventors: Yuuki DOI, Hirokazu Fujimaki
  • Publication number: 20100073039
    Abstract: An H-bridge circuit includes a lower-arm field-effect transistor and a current supplying element that turns on when the drain of the lower-arm field-effect transistor is negatively biased due to regenerative current. When turned on, the current supplying element conducts current from the source to the drain of the lower-arm field-effect transistor, in parallel with a parasitic diode inherent in the lower-arm field effect transistor. The current supplying element competes with other parasitic elements that conduct current from peripheral circuitry to the drain of the lower-arm field-effect transistor, thereby reducing the amount of such current drawn through the peripheral circuitry and lessening the impact of the regenerative current on the peripheral circuits.
    Type: Application
    Filed: September 23, 2009
    Publication date: March 25, 2010
    Applicant: OKI SEMICONDUCTOR CO., LTD.
    Inventors: Miyuki Kanai, Hirokazu Fujimaki, Takeshi Shimizu
  • Patent number: 7663241
    Abstract: A semiconductor device comprises a substrate, a first conductive film, a first insulation film, a second insulation film, a second conductive film, and a third conductive film. The first conductive film is formed on the substrate. The first insulation film is formed on the first conductive film and has a first opening. The first opening is formed as having multiple crossing trenches each having a predetermined width. The second insulation film is formed on the sides and bottom of the first opening. The second conductive film is formed on the second insulation film in the interior of the first opening. The third conductive film is formed on the second insulation film and the second conductive film.
    Type: Grant
    Filed: October 3, 2007
    Date of Patent: February 16, 2010
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Hirokazu Fujimaki
  • Publication number: 20090199896
    Abstract: According to the present invention, a dye-sensitized solar cell includes a conductive substrate, which is transparent; and a photovoltaic (photoelectric exchange) layer formed on the conductive substrate. The photovoltaic layer comprises a lighter (brighter) region and a darker region therein.
    Type: Application
    Filed: January 15, 2009
    Publication date: August 13, 2009
    Applicant: OKI SEMICONDUCTOR CO., LTD.
    Inventors: Hirokazu Fujimaki, Hidehiro Higashino
  • Publication number: 20080042286
    Abstract: A semiconductor device comprises a substrate, a first conductive film, a first insulation film, a second insulation film, a second conductive film, and a third conductive film. The first conductive film is formed on the substrate. The first insulation film is formed on the first conductive film and has a first opening. The first opening is formed as having multiple crossing trenches each having a predetermined width. The second insulation film is formed on the sides and bottom of the first opening. The second conductive film is formed on the second insulation film in the interior of the first opening. The third conductive film is formed on the second insulation film and the second conductive film.
    Type: Application
    Filed: October 3, 2007
    Publication date: February 21, 2008
    Applicant: OKI ELECTRIC INDUSTRY CO., LTD.
    Inventor: Hirokazu Fujimaki
  • Publication number: 20070251574
    Abstract: In a dye-sensitized solar cell comprising a first electrode having a photoelectric conversion layer, a second electrode disposed so as to oppose the first electrode, and electrolyte filled at least in between the first electrode and second electrode, the first electrode is constructed with a plurality of first electrode layers disposed superposed in a direction that opposes to the second electrode.
    Type: Application
    Filed: March 30, 2007
    Publication date: November 1, 2007
    Applicant: OKI ELECTRIC INDUSTRY CO. LTD.
    Inventors: Hirokazu Fujimaki, Minoru Watanabe
  • Publication number: 20070246096
    Abstract: A dye-sensitized solar cell, comprising: a light-transmission substrate; a plurality of auxiliary electrodes, formed on the light-transmission substrate; an oxide semiconductor layer which is formed on the light-transmission substrate so as to cover the plurality of auxiliary electrodes directly; and dyes, adhered to the oxide semiconductor layer. Each of electrons, excited at the dyes, is transferred to a nearest auxiliary electrode over a distance “C”, which is smaller than a thickness “B” of the oxide semiconductor layer.
    Type: Application
    Filed: February 8, 2007
    Publication date: October 25, 2007
    Applicant: OKI ELECTRIC INDUSTRY CO., LTD.
    Inventor: Hirokazu Fujimaki
  • Patent number: 7285455
    Abstract: A method of producing a semiconductor device includes the steps of: preparing a double SOI substrate, forming a deep trench, filling the deep trench, forming an opening, forming a cavity, depositing a polycrystalline silicon layer, and forming a bipolar transistor.
    Type: Grant
    Filed: December 14, 2006
    Date of Patent: October 23, 2007
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Hirokazu Fujimaki
  • Publication number: 20070090400
    Abstract: A method of producing a semiconductor device includes the steps of: preparing a double SOI substrate, forming a deep trench, filling the deep trench, forming an opening, forming a cavity, depositing a polycrystalline silicon layer, and forming a bipolar transistor.
    Type: Application
    Filed: December 14, 2006
    Publication date: April 26, 2007
    Inventor: Hirokazu Fujimaki
  • Publication number: 20070085139
    Abstract: A semiconductor device capable of preventing the occurrence of stress in a field region, and to prevent dislocation, caused by the stress, in the active region is provided. The semiconductor device includes a support substrate; an active island region having single crystal silicon being formed on the support substrate; a CVD film being configured to surround a periphery of the active island region; a boundary between the active island region and the CVD film having an interstice portion being formed therein, the interstice portion being configured to surround the single crystal silicon layer; and a first insulating film being configured to bury the interstice portion.
    Type: Application
    Filed: November 7, 2006
    Publication date: April 19, 2007
    Applicant: OKI ELECTRIC INDUSTRY CO., LTD.
    Inventor: Hirokazu Fujimaki
  • Patent number: 7205587
    Abstract: A method of producing a semiconductor device includes the steps of: preparing a double SOI substrate, forming a deep trench, filling the deep trench, forming an opening, forming a cavity, depositing a polycrystalline silicon layer, and forming a bipolar transistor.
    Type: Grant
    Filed: July 28, 2005
    Date of Patent: April 17, 2007
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Hirokazu Fujimaki
  • Publication number: 20070063198
    Abstract: A semiconductor device capable of preventing the occurrence of stress in a field region, and to prevent dislocation, caused by the stress, in the active region is provided. The semiconductor device includes a support substrate; an active island region having single crystal silicon being formed on the support substrate; a CVD film being configured to surround a periphery of the active island region; a boundary between the active island region and the CVD film having an interstice portion being formed therein, the interstice portion being configured to surround the single crystal silicon layer; and a first insulating film being configured to bury the interstice portion.
    Type: Application
    Filed: November 7, 2006
    Publication date: March 22, 2007
    Applicant: OKI ELECTRIC INDUSTRY CO., LTD.
    Inventor: Hirokazu FUJIMAKI
  • Publication number: 20060267098
    Abstract: A semiconductor device comprises a substrate, a first conductive film, a first insulation film, a second insulation film, a second conductive film, and a third conductive film. The first conductive film is formed on the substrate. The first insulation film is formed on the first conductive film and has a first opening. The first opening is formed as having multiple crossing trenches each having a predetermined width. The second insulation film is formed on the sides and bottom of the first opening. The second conductive film is formed on the second insulation film in the interior of the first opening. The third conductive film is formed on the second insulation film and the second conductive film.
    Type: Application
    Filed: March 29, 2006
    Publication date: November 30, 2006
    Applicant: OKI ELECTRIC INDUSTRY CO., LTD.
    Inventor: Hirokazu FUJIMAKI