Patents by Inventor Hirokazu Fujimaki

Hirokazu Fujimaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7132729
    Abstract: The present invention provides a semiconductor device formed with a diode array together with bipolar transistors, which is capable of preventing the occurrence of crystal defects developed in cross patterns in deep trench regions and improving device yields, and a method of manufacturing the semiconductor device. A semiconductor device includes a LOCOS oxide film which isolates a plurality of diodes in an X direction, and deep trenches which isolate the plurality of diodes in a Y direction. The depth of each of the deep trenches is deeper than a high density layer embedded below a collector layer of each bipolar transistor. A shallow trench may be used as an alternative to the LOCOS oxide film.
    Type: Grant
    Filed: August 31, 2004
    Date of Patent: November 7, 2006
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Hirokazu Fujimaki
  • Patent number: 7026221
    Abstract: A method of forming a semiconductor device, including forming first and second semiconductor layers of first conductivity type each disposed in a transistor forming region spaced apart from each other by a predetermined distance, so that the first semiconductor layer has a concentration higher than the second semiconductor layer; vapor-phase diffusing an impurity of second conductivity type into side faces of the second semiconductor layer which are exposed in the spaced region; embedding a non-doped semiconductor layer between the first and second semiconductor layers in the spaced region; and performing heat treatment to change the non-doped semiconductor layer into first conductivity type, a region of the vapor phase diffused side faces into the first conductivity type, and another region of the vapor phase diffused side faces into an intrinsic base region.
    Type: Grant
    Filed: January 29, 2003
    Date of Patent: April 11, 2006
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Hirokazu Fujimaki
  • Publication number: 20060046409
    Abstract: A method of producing a semiconductor device includes the steps of: preparing a double SOI substrate, forming a deep trench, filling the deep trench, forming an opening, forming a cavity, depositing a polycrystalline silicon layer, and forming a bipolar transistor.
    Type: Application
    Filed: July 28, 2005
    Publication date: March 2, 2006
    Inventor: Hirokazu Fujimaki
  • Publication number: 20050199980
    Abstract: The present invention provides a semiconductor device formed with a diode array together with bipolar transistors, which is capable of preventing the occurrence of crystal defects developed in cross patterns in deep trench regions and improving device yields, and a method of manufacturing the semiconductor device. A semiconductor device includes a LOCOS oxide film which isolates a plurality of diodes in an X direction, and deep trenches which isolate the plurality of diodes in a Y direction. The depth of each of the deep trenches is deeper than a high density layer embedded below a collector layer of each bipolar transistor. A shallow trench may be used as an alternative to the LOCOS oxide film.
    Type: Application
    Filed: August 31, 2004
    Publication date: September 15, 2005
    Inventor: Hirokazu Fujimaki
  • Publication number: 20050059220
    Abstract: A semiconductor device capable of preventing the occurrence of stress in a field region, and to prevent dislocation, caused by the stress, in the active region is provided. A method for producing a semiconductor includes: forming an active island region (10) on or above an support substrate; forming a field region (20) surrounding a periphery of the active island region (10); forming an interstice portion (112) at boundary between the active island region (10) and the field region (20); subjecting the field region (20) to heat treatment to eject a residual matter to be evaporated after forming the interstice portion (112); and burying the interstice portion (112) by thermal oxidation.
    Type: Application
    Filed: September 10, 2004
    Publication date: March 17, 2005
    Applicant: Oki Electric Co., Ltd.
    Inventor: Hirokazu Fujimaki
  • Patent number: 6780725
    Abstract: A method of manufacturing vertical NPN and PNP transistors on a substrate includes forming a first oxide film, a P-polycrystal silicon film, and a second oxide film successively on N-silicon epitaxial film on the substrate. An opening is made in the first oxide film to expose the N-silicon epitaxial film and a bottom of the P-polycrystal silicon film anisotropically etching the second oxide film and the P-polycrystal silicon film, and then isotropically etching the exposed first oxide film. A part of the opening is plugged by growing a selective epitaxial layer including a P-monocrystal layer from the surface of the N-silicon epitaxial film, and growing a polycrystal layer from the bottom of the P-polycrystal silicon film. Then, within a PNP transistor section, position and impurity concentration of a P-N junction are adjusted by self-aligned implanting or diffusing of P-impurities into the N-silicon epitaxial layer through the opening.
    Type: Grant
    Filed: November 21, 2002
    Date of Patent: August 24, 2004
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Hirokazu Fujimaki
  • Patent number: 6709941
    Abstract: In a method for manufacturing a semiconductor device, an N type single-crystal silicon substrate having a first silicon oxide film and a P type poly-crystal silicon layer is provided. A silicon nitride film is formed on the P type poly-crystal silicon layer. A side wall of the silicon nitride film is formed in an opening in the P type poly-crystal silicon layer above a portion expected to provide an active region. The first silicon oxide film has an opening therein which is larger than the opening formed in the P type poly-crystal silicon layer. Then, an N type IV-group semiconductor mixed crystal layer having a smaller band gap than silicon to a desired thickness is grown on the single-crystal silicon substrate on which a surface of the portion expected to provide said active region is exposed. A non-doped single-crystal silicon layer is grown on the IV-group semiconductor mixed crystal layer to a desired thickness.
    Type: Grant
    Filed: November 6, 2002
    Date of Patent: March 23, 2004
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Hirokazu Fujimaki
  • Publication number: 20030219952
    Abstract: A method of manufacturing a semiconductor device in which a vertical NPN transistor and a vertical PNP transistor are formed on the same substrate including a first step of forming a first oxide film, a P-polycrystal silicon film, and a second oxide film in succession on an N-silicon epitaxial film formed on a substrate, a second step of making an opening in the first oxide film through which a surface of the N-silicon epitaxial film and a part of a bottom of the P-polycrystal silicon film are exposed by anaisotropically etching the second oxide film and the P-polycrystal silicon film, and then isotropically etching the first oxide film that has been exposed, a third step of plugging at least a part of the opening by growing a selective epitaxial layer including a P-monocrystal layer from the surface of the N-silicon epitaxial film, and growing a polycrystal layer from the part of the bottom of the P-polycrystal silicon film, and a fourth step of adjusting, within a PNP transistor section, a P-N junction's po
    Type: Application
    Filed: November 21, 2002
    Publication date: November 27, 2003
    Inventor: Hirokazu Fujimaki
  • Publication number: 20030203582
    Abstract: The present invention provides a method of forming a semiconductor device, includes processes for forming first and second semiconductor layers of first conductivity type each disposed in a transistor forming region with both being spaced a predetermined distance from each other, and forming the first semiconductor layer so as to have a concentration higher than the second semiconductor layer; a vapor-phase diffusing an impurity of second conductivity type into side faces of the second semiconductor layer, which are exposed in the spaced region; embedding a non-doped semiconductor layer between the first and second semiconductor layers in the spaced region; and a step for performing heat treatment until the non-doped semiconductor layer is brought to the first conductivity type, part of a region for the second conductivity type impurity diffused into sidewalls of the second semiconductor layer is brought to the first conductivity type, and the other region for the second conductivity type impurity is brought
    Type: Application
    Filed: January 29, 2003
    Publication date: October 30, 2003
    Inventor: Hirokazu Fujimaki
  • Publication number: 20030186562
    Abstract: In a method for manufacturing a semiconductor device, an N type single-crystal silicon substrate having a first silicon oxide film and a P type poly-crystal silicon layer is provided. A silicon nitride film is formed on the P type poly-crystal silicon layer. A side wall of the silicon nitride film is formed in an opening in the P type poly-crystal silicon layer above a portion expected to provide an active region. The first silicon oxide film has an opening therein which is larger than the opening formed in the P type poly-crystal silicon layer. Then, an N type IV-group semiconductor mixed crystal layer having a smaller band gap than silicon to a desired thickness is grown on the single-crystal silicon substrate on which a surface of the portion expected to provide said active region is exposed. A non-doped single-crystal silicon layer is grown on the IV-group semiconductor mixed crystal layer to a desired thickness.
    Type: Application
    Filed: November 6, 2002
    Publication date: October 2, 2003
    Inventor: Hirokazu Fujimaki
  • Patent number: 6548371
    Abstract: A method for manufacturing a semiconductor device in which one active area and another active area formed on an element substrate are electrically isolated from each other includes a first step in which a groove-like area is formed at the element substrate by performing a treatment under conditions whereby the etching rate on a surface {100} is higher than the etching rate on a surface {111} in the area between the one active area and the another active area, and a second step in which the bottom surface of the groove-like area is etched through anisotropic etching. The first step is implemented within a 20 Torr hydrogen gas atmosphere that contains hydrogen chloride gas, and at a temperature of 800 centigrade. The shape of the corner portion formed at the upper end of the trench becomes widened until the angle formed by the side wall and the surface {111} is approximately 144.7 degrees, thereby greatly reducing the concentration of stress at the corner portion.
    Type: Grant
    Filed: April 1, 1999
    Date of Patent: April 15, 2003
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Hirokazu Fujimaki
  • Publication number: 20020076898
    Abstract: A method for manufacturing a semiconductor device in which one active area and another active area formed on an element substrate are electrically isolated from each other includes a first step in which a groove-like area is formed at the element substrate by performing a treatment under conditions whereby the etching rate on a surface {100} is higher than the etching rate on a surface {111} in the area between the one active area and the another active area, and a second step in which the bottom surface of the groove-like area is etched through anisotropic etching. The first step is implemented within a 20 Torr hydrogen gas atmosphere that contains hydrogen chloride gas, and at a temperature of 800 centigrade. The shape of the corner portion formed at the upper end of the trench becomes widened until the angle formed by the side wall and the surface {111} is approximately 144.7 degrees, thereby greatly reducing the concentration of stress at the corner portion.
    Type: Application
    Filed: April 1, 1999
    Publication date: June 20, 2002
    Inventor: HIROKAZU FUJIMAKI