Abstract: An electro-static discharge protection circuit and a semiconductor device having the same is disclosed. The electro-static discharge protection circuit has a current control circuit. The current control circuit has a first capacitive element. When the external source voltage is applied to the external source voltage supply line, the booster circuit in the internal circuitry boosts the internal source voltage of the internal source voltage supply line. The external source voltage becomes transiently greater than the internal source voltage at the early stage of the boosting step when the booster circuit boosts the internal source voltage based on the external source voltage.

Abstract: A physical analysis (S2) of the elements used in an ESD protection circuit is performed; parameters of the elements that have a comparatively large effect on ESD protection characteristics are extracted as key parameters (S4); and a mixed-mode device-circuit simulation of the ESD protection circuit is performed, using the key parameters, to optimize the key parameters (S5). This can shorten the time required for designing an ESD circuit.

Abstract: A semiconductor device includes a laminated substrate; a removal portion; a cavity; a first semiconductor element; and a second semiconductor element. In the laminated substrate, a bulk layer, an insulating layer, and a semiconductor layer are laminated in this order from a bottom. The laminated substrate includes a first area, a second area adjacent to the first area, and a third area adjacent to the second area in each of the layers. The semiconductor layer, the insulating layer, and an upper portion of the bulk layer in the first area are removed to form the removal portion. A part of the bulk layer in the second area is removed to form the cavity adjacent to the removal portion. The first semiconductor element is formed in the bulk layer in the removal portion as an ESD protection element. The second semiconductor element is formed partially in the semiconductor layer in the second area.

Abstract: An evaluation TEG for evaluating a semiconductor device including an SOI structure and a LOCOS having a birdbeak portion comprises two electrodes 10 and 20 having different electrode widths sufficiently large to disregard the length of the LOCOS birdbeak portion and an electrode 30 having an extremely small width substantially equal to the length of the birdbeak portion. All the electrode have the same length and are connected to test pads 10a, 20a, and 30a, respectively. The capacitance of a parasitic transistor is easily extracted by using the evaluation TEG and the evaluation of parameters causing the hump characteristics is become possible.

Abstract: A method for modeling a device and a network to be analyzed in a complex simulation. The modeling method includes a device extraction step for extracting the structure of each of a plurality of devices included in the network to create device models showing the individual extracted structures, a device connection step for connecting the respective device models through the intermediary of an insulating portion for cutting off the electrical connection between the respective device models, and a circuit connection step for connecting a network model showing the network portion, from which the plurality of devices extracted in the device extraction step have been excluded, to a predetermined device model among the connected device models.

Abstract: The present invention provides a method of manufacturing an ESD protection device with a gate electrode structure that reduces surge voltage applied to a gate insulating film and inhibits destruction of the gate insulating film. A method of manufacturing a semiconductor device includes steps of preparing a support substrate, forming a device region and a device-separation region on the support substrate, forming a gate insulating film in the device region, forming a first gate electrode on the gate insulating film, implanting a first impurity ion into the first gate electrode, and decreasing a first impurity ion concentration by implanting a second impurity ion with a polar character, which is opposite from that of the first impurity ion, into the first gate electrode.

Abstract: The present invention provides a method of evaluating a semiconductor device having an ESD protective element, wherein a MOSFET is formed on the same substrate, comprising a step (electric characteristic measurement) for measuring an electric characteristic of the MOSFET, a step (snapback characteristic measurement) for measuring a snapback characteristic of the MOSFET, a step (impurity profile extraction) for extracting an impurity profile of the MOSFET from the electric characteristic and snapback characteristic of the MOSFET by using an inverse modeling technique, and a step (impurity profile adaptation) for causing the extracted impurity profile of the MOSFET and an impurity profile of the ESD protective element to correspond to each other, whereby the impurity profile of the ESD protective element is evaluated from the electric characteristic.

Abstract: An ESD protection device modeling method of modeling an electrical characteristic of an electrostatic discharge (ESD) protection device for simulating a circuit that include the ESD protection device, comprising the steps of (114) setting a parameter of at least one specific element that affects the electrical characteristic of the ESD protection device; and (116) modeling the electrical characteristic of the ESD protection device with the parameter of the specific element.

Abstract: A method for modeling a device and a network to be analyzed in a complex simulation. The modeling method includes a device extraction step for extracting the structure of each of a plurality of devices included in the network to create device models showing the individual extracted structures, a device connection step for connecting the respective device models through the intermediary of an insulating portion for cutting off the electrical connection between the respective device models, and a circuit connection step for connecting a network model showing the network portion, from which the plurality of devices extracted in the device extraction step have been excluded, to a predetermined device model among the connected device models.

Abstract: An evaluation TEG for evaluating a semiconductor device including an SOI structure and a LOCOS having a birdbeak portion comprises two electrodes 10 and 20 having different electrode widths sufficiently large to disregard the length of the LOCOS birdbeak portion and an electrode 30 having an extremely small width substantially equal to the length of the birdbeak portion. All the electrode have the same length and are connected to test pads 10a, 20a, and 30a, respectively. The capacitance of a parasitic transistor is easily extracted by using the evaluation TEG and the evaluation of parameters causing the hump characteristics is become possible.

Abstract: A semiconductor modeling method capable of simulating impurity pileup at a Si/SiO2 interface, and analyzing electrical characteristics (for example, substrate bias dependency) of a semiconductor, dependent on impurity concentration, under high speed calculation. A portion of impurities in a Si substrate region is caused to migrate to the Si/SiO2 interface, there by constituting an impurity pileup part. With such a method, it becomes possible to express the impurity pileups at the Si/SiO2 interface, which could not be expressed with the use of the conventional Fair model, without finding the solution to diffusion equations associated with point defects, that is without the use of the conventional pair diffusion model.

Abstract: In a profile extraction method, a long channel profile is first extracted through an initial profile generating stage and a long channel profile extraction stage. In a following two-dimensional profile extraction stage, a two-dimensional channel profile extraction stage and a source/drain profile extraction stage are repeated to extract an optimized two-dimensional channel profile and an optimized source/drain profile. In the two-dimensional channel profile extraction stage, a two-dimensional channel profile is extracted from the gate length dependency of the threshold voltage. In addition, in the source/drain profile extraction stage, a source/drain profile is extracted from the substrate bias voltage dependency of the threshold voltage—gate length characteristics.

Abstract: A SOI structure semiconductor device includes a silicon substrate (1), an insulating oxide layer (2) formed on the silicon substrate (1), a SOI layer (3) formed on the insulating oxide layer (2) a LOCOS oxide layer (4) formed on the insulating oxide layer (2) and contacting with the SOI layer (3) in order to insulate the SOI layer (3), a gate insulation layer (5) formed on the SOI layer (3) and a gate electrode (6) formed on the gate insulation layer (5). The SOI layer (3) has a sectional triangle portion (10) contacting with the LOCOS oxide layer (4). The sectional triangle has an oblique side (12) as a boundary between the SOI layer (4) and the LOCOS oxide layer (3), a height side (13) equal to the thickness of the SOI layer (3) and a base on the lower boundary of the SOI layer (3), in which the ratio of the height side (13) to the base is 4:1 or less.

Abstract: There is disclosed a method for using a computer to calculate a pileup state of an impurity in an interface between an Si layer in which a source and a drain are formed, and an SiO2 layer brought in contact with the Si layer at a high speed. First, data is set assuming that the Si layer is constituted of a plurality of cells. Subsequently, the impurity is moved to a pileup position of the interface from each cell, and an amount of impurity piled up in each pileup position of the interface is calculated. In this case, a mass of the impurity moving to the interface from each cell is determined as a function of a distance to each pileup position from each cell, and a distance to a source or a drain closest to the cell.

Abstract: A SOI structure semiconductor device includes a silicon substrate (1), an insulating oxide layer (2) formed on the silicon substrate (1), a SOI layer (3) formed on the insulating oxide layer (2) a LOCOS oxide layer (4) formed on the insulating oxide layer (2) and contacting with the SOI layer (3) in order to insulate the SOI layer (3), a gate insulation layer (5) formed on the SOI layer (3) and a gate electrode (6) formed on the gate insulation layer (5). The SOI layer (3) has a sectional triangle portion (10) contacting with the LOCOS oxide layer (4). The sectional triangle has an oblique side (12) as a boundary between the SOI layer (4) and the LOCOS oxide layer (3), a height side (13) equal to the thickness of the SOI layer (3) and a base on the lower boundary of the SOI layer (3), in which the ratio of the height side (13) to the base is 4:1 or less.

Abstract: The invention provides a semiconductor modeling method capable of simulating impurity pileup at a Si/SiO2 interface, and analyzing electrical characteristics (for example, substrate bias dependency) of a semiconductor, dependent on impurity concentration, under high speed calculation. A portion of impurities in a Si substrate region is caused to migrate to the Si/SiO2 interface, thereby constituting an impurity pileup part. With such a method, it becomes possible to express the impurity pileups at the Si/SiO2 interface, which could not be expressed with the use of the conventional Fair model, without finding the solution to diffusion equations associated with point defects (that is, without the use of the conventional pair diffusion model).

Abstract: A SOI structure semiconductor device includes a silicon substrate (1), an insulating oxide layer (2) formed on the silicon substrate (1), a SOI layer (3) formed on the insulating oxide layer (2) a LOCOS oxide layer (4) formed on the insulating oxide layer (2) and contacting with the SOI layer (3) in order to insulate the SOI layer (3), a gate insulation layer (5) formed on the SOI layer (3) and a gate electrode (6) formed on the gate insulation layer (5). The SOI layer (3) has a sectional triangle portion (10) contacting with the LOCOS oxide layer (4). The sectional triangle has an oblique side (12) as a boundary between the SOI layer (4) and the LOCOS oxide layer (3), a height side (13) equal to the thickness of the SOI layer (3) and a base on the lower boundary of the SOI layer (3), in which the ratio of the height side (13) to the base is 4:1 or less.

Abstract: A chromaticity meter measures chromaticity of light output for each of picture elements selected. Calculated from the measurement is corrective data on each of RGB colors, which in turn used to calculate corrective data on each of RGB at unselected picture elements. In this method, original video signals for each of RGB colors will be correctively modulated based on the thus obtained corrective data. A projected image displaying apparatus is constructed such that adjustment of chromaticity as to white as well as to black from the measurement by the chromaticity meter of chromaticity throughout the entire image, is carried out uniformly and reliably by automatic control using a microcomputer so as to determine optimal condition for correctively modulating the original video signal. This apparatus further includes means for storing the thus obtained optimal condition in a non-volatile memory.

Abstract: A cationic electrodeposition coating composition comprising[A] a neutralization product or a quaternary ammonium salt of a comb-shaped copolymer obtained by copolymerizing (a) 3 to 90 parts by weight of an ethylenically unsaturated monomer having a hydrocarbon chain with at least 8 carbon atoms at the molecular ends, (b) 1 to 50 parts by weight of at least one cationic (meth)acrylic monomer selected from the group consisting of aminoalkyl (meth)acrylates, aminoalkyl (meth)acrylamides (meth)acrylates containing a quaternary ammonium salt group and (meth)acrylamides containing a quaternary ammonium salt group, (c) 1 to 60 parts by weight of an alpha,beta-ethylenically unsaturated monomer other than the monomer (b), and (d) 0 to 95 parts by weight of an alpha,beta-ethylenically unsaturated monomer other than the monomers (a), (b) and (c),[B] a cationic epoxy resin capable of being dissolved or dispersed in water, and[C] a pigment.

Abstract: An electrodeposition coating composition containing blocked isocyanate groups comprising at least one dialkyltin aromatic carboxylic acid salt represented by the following formula ##STR1## wherein R represents an alkyl group having 1 to 12 carbon atoms, and R.sup.1 represents a hydrogen atom or an alkyl group having 1 to 4 carbon atoms.