Patents by Inventor Hirokazu Kato

Hirokazu Kato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160042942
    Abstract: A pattern forming method includes forming a spin on dielectric film on a substrate, washing the spin on dielectric film by using a washing liquid, drying a surface of the spin on dielectric film after the washing, forming a photosensitive film on the dried coating type insulation film, emitting energy rays to a predetermined position of the photosensitive film in order to form a latent image on the photosensitive film, developing the photosensitive film in order to form a photosensitive film pattern which corresponds to the latent image, and processing the spin on dielectric film with the photosensitive film pattern serving as a mask.
    Type: Application
    Filed: October 22, 2015
    Publication date: February 11, 2016
    Inventors: Tomoyuki TAKEISHI, Hirokazu KATO, Shinichi ITO
  • Patent number: 9252088
    Abstract: A semiconductor device is inhibited from being degraded in reliability. The semiconductor device has a tab including a top surface, a bottom surface, and a plurality of side surfaces. Each of the side surfaces of the tab has a first portion continued to the bottom surface of the tab, a second portion located outwardly of the first portion and continued to the top surface of the tab, and a third portion located outwardly of the second portion and continued to the top surface of the tab to face the same direction as each of the first and second portions. In planar view, the outer edge of the semiconductor chip is located between the third portion and the second portion of the tab, and the outer edge of an adhesive material fixing the semiconductor chip to the tab is located between the semiconductor chip and the second portion.
    Type: Grant
    Filed: November 12, 2014
    Date of Patent: February 2, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Keita Takada, Tadatoshi Danno, Hirokazu Kato
  • Patent number: 9202722
    Abstract: A pattern forming method includes forming a spin on dielectric film on a substrate, washing the spin on dielectric film by using a washing liquid, drying a surface of the spin on dielectric film after the washing, forming a photosensitive film on the dried coating type insulation film, emitting energy rays to a predetermined position of the photosensitive film in order to form a latent image on the photosensitive film, developing the photosensitive film in order to form a photosensitive film pattern which corresponds to the latent image, and processing the spin on dielectric film with the photosensitive film pattern serving as a mask.
    Type: Grant
    Filed: April 22, 2014
    Date of Patent: December 1, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomoyuki Takeishi, Hirokazu Kato, Shinichi Ito
  • Patent number: 9142555
    Abstract: Provided is a semiconductor device having improved performance. A semiconductor substrate is formed with unit LDMOSFET elements. The unit LDMOSFET elements have respective source regions electrically coupled to each other via a first source interconnect line and a second source interconnect line. The unit LDMOSFET elements have respective gate electrodes electrically coupled to each other via a first gate interconnect line and also electrically coupled to a second gate interconnect line in the same layer as that of the second source interconnect line via the first gate interconnect line. The unit LDMOSFET elements have respective drain regions electrically coupled to a back surface electrode via a conductive plug embedded in a trench of the semiconductor substrate. Each of the first source interconnect line and the first gate interconnect line has a thickness smaller than that of the second source interconnect line. Over the plug, the first gate interconnect line extends.
    Type: Grant
    Filed: November 20, 2014
    Date of Patent: September 22, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshinori Yoshida, Hirokazu Kato, Tsuyoshi Kachi, Keisuke Furuya
  • Publication number: 20150219058
    Abstract: A control device of a vehicle includes: a first gear connected to a crankshaft of an engine; a second gear capable of engaging the first gear; an actuator configure to move the second gear up to a position where the second gear engages the first gear; a motor configured to cause the second gear to rotate; and a controller configured to, when the engine is cranked by driving of the motor in response to elapsing of a predefined period after the actuator is actuated in response to a startup request signal of the engine, adjust a length of the predefined period on the basis of an operating state of a driver and a state of the vehicle at the time of reception of the startup request signal.
    Type: Application
    Filed: November 18, 2013
    Publication date: August 6, 2015
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Hirokazu Kato, Junpei Kakehi
  • Publication number: 20150204818
    Abstract: A damage detecting device according to one aspect of the present invention comprises a first speed generator, a second speed generator, a first waveform shaping section, a second waveform shaping section, and a determining section. The determining section compares a second rectangular wave shaped by the second waveform shaping section and a first rectangular wave shaped by the first waveform shaping section and, if the first rectangular wave is not output while the second rectangular wave is output, determines that a supporting device for an armature shaft is damaged or worn.
    Type: Application
    Filed: August 8, 2013
    Publication date: July 23, 2015
    Applicant: CENTRAL JAPAN RAILWAY COMPANY
    Inventors: Mamoru Tanaka, Masayuki Ueno, Yoshiya Watanabe, Hirokazu Kato
  • Patent number: 9081274
    Abstract: According to one embodiment, a pattern forming method includes, forming a first mask on a film to be processed, forming a guide that has a pattern including first openings and second openings, forming a second mask which covers the first openings and does not cover the second openings, etching the first mask using the second mask and the guide as a mask, removing the second mask, applying a self-assembling material into the first openings and the second openings, heating the self-assembling material to form a self-assembled pattern including a first polymer portion and a second polymer portion, etching the first polymer portion, etching the first mask using the second polymer portion and the guide as a mask, and processing the film to be processed using the first mask as a mask.
    Type: Grant
    Filed: February 14, 2014
    Date of Patent: July 14, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hirokazu Kato
  • Publication number: 20150194894
    Abstract: A trench MOSFET is disclosed that includes a semiconductor substrate having a vertically oriented trench containing a gate. The trench MOSFET further includes a source, a drain, and a conductive element. The conductive element, like the gate is contained in the trench, and extends between the gate and a bottom of the trench. The conductive element is electrically isolated from the source, the gate, and the drain. When employed in a device such as a DC-DC converter, the trench MOSFET may reduce power losses and electrical and electromagnetic noise.
    Type: Application
    Filed: March 24, 2015
    Publication date: July 9, 2015
    Inventors: Tetsuo Sato, Tomoaki Uno, Hirokazu Kato, Nobuyoshi Matsuura
  • Patent number: 9073436
    Abstract: A plurality of power conversion apparatuses disposed in a traveling direction of a plurality of vehicles coupled to one another each includes a conversion unit to convert electric power; a heat dissipation unit to dissipate heat that is generated in the conversion unit to a traveling wind; and a control unit to control the electric power to be converted. A control unit in a first power conversion apparatus is disposed forward, in the traveling direction, of a heat dissipation unit in the first power conversion apparatus, and increases or decreases electric power to be converted in a conversion unit of the first power conversion apparatus in accordance with at least one of information of a number of other heat dissipation units dissipating heat to the traveling wind and information of a distance to a forwardly adjacent one of the other heat dissipation units in the traveling direction.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: July 7, 2015
    Assignee: CENTRAL JAPAN RAILWAY COMPANY
    Inventors: Masayuki Ueno, Kenji Sato, Hirokazu Kato
  • Patent number: 9054450
    Abstract: A connector adapted to: (a) extend through an opening in a board to protrude from both a top surface of the board and a bottom surface of the board, (b) secure the connector to the board, and (c) electrically connect a power supply to a terminal on the board. The connector includes a housing having: (a) a leg section, (b) a head section at a first end of the leg section of the housing, and (c) a receiving recess at a second end of the leg section adapted to receive the power supply board. This connector also includes an elastically deformable retainer piece having: a) a cantilever spring section fixed at a first end to the leg section of the housing and adapted to be below the bottom surface of the board, and (b) an apex section at a second end of the cantilever spring section adapted to bear against the bottom surface of the board. This connector further includes an elastically deformable contact protruding from the head section of the housing adapted to contact the terminal of the board.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: June 9, 2015
    Assignee: Tyco Electronics Japan G.K.
    Inventors: Taisuke Nagasaki, Hirokazu Kato
  • Publication number: 20150156443
    Abstract: According to one embodiment, an electronic apparatus includes a data receiver, processing circuitry and an operation information receiver. The data receiver receives first data for displaying an image. The processing circuitry displays, using the first data, the image on a screen of a display. The operation information receiver receives operation information indicating that one of a plurality of buttons provided at a remote control is pressed. The processing circuitry displays, based on the operation information, an enlarged image of a first area of a plurality of divided areas of the image on the screen.
    Type: Application
    Filed: October 7, 2014
    Publication date: June 4, 2015
    Inventors: Kenichi Taniuchi, Kazuhiko Kashiwagi, Akira Kumagai, Yuuichiro Aso, Hirokazu Kato
  • Publication number: 20150151329
    Abstract: In a pattern forming method according to the present embodiment, a first guide layer having a first pattern is formed above a base material. A second guide layer having a second pattern intersecting the first pattern is formed. A directed self-assembly material is introduced in a concave portion surrounded by the first and second guide layers. A directed self-assembly pattern having a diameter which is smaller than an opening diameter of the concave portion is formed in the concave portion by causing the directed self-assembly material to be directed self-assembled.
    Type: Application
    Filed: February 27, 2014
    Publication date: June 4, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Ayako KAWANISHI, Hirokazu Kato, Hiroki Yonemitsu, Yusuke Kasahara
  • Publication number: 20150145025
    Abstract: Provided is a semiconductor device having improved performance. A semiconductor substrate is formed with unit LDMOSFET elements. The unit LDMOSFET elements have respective source regions electrically coupled to each other via a first source interconnect line and a second source interconnect line. The unit LDMOSFET elements have respective gate electrodes electrically coupled to each other via a first gate interconnect line and also electrically coupled to a second gate interconnect line in the same layer as that of the second source interconnect line via the first gate interconnect line. The unit LDMOSFET elements have respective drain regions electrically coupled to a back surface electrode via a conductive plug embedded in a trench of the semiconductor substrate. Each of the first source interconnect line and the first gate interconnect line has a thickness smaller than that of the second source interconnect line. Over the plug, the first gate interconnect line extends.
    Type: Application
    Filed: November 20, 2014
    Publication date: May 28, 2015
    Inventors: YOSHINORI YOSHIDA, HIROKAZU KATO, TSUYOSHI KACHI, Keisuke FURUYA
  • Patent number: 9040429
    Abstract: A pattern formation method comprises a process of forming a resist pattern with an opening that exposes a first region of a glass film arranged on a substrate through a base film; a process of forming a neutralization film above the glass film; a process of forming a directed self-assembly material layer containing a first segment and a second segment above the glass film; a process of microphase separating the directed self-assembly material layer to form a directed self-assembly pattern containing a first part that includes the first segment and a second part that includes the second segment; and a process of removing either the first part or the second part and using the other as a mask to process the base film.
    Type: Grant
    Filed: March 4, 2013
    Date of Patent: May 26, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hirokazu Kato, Ayako Kawanishi
  • Patent number: 9034766
    Abstract: According to one embodiment, a pattern formation method includes: forming a first guide layer having of first openings exposing a surface of an underlayer, and the first openings being arranged in a first direction; forming a second guide layer on the underlayer and on the first guide layer, the second guide layer extending in the first direction, the second guide layer dividing each of the first openings into the first opening portion and the second opening portion, and the second guide layer being sandwiched by a first opening portion and a second opening portion; forming a block copolymer layer in each of the first opening portion and the second opening portion; forming a first layer and a second layer surrounded by the first layer in each of the first opening portion and the second opening portion by phase-separating the block copolymer layer; and removing the second layer.
    Type: Grant
    Filed: February 12, 2014
    Date of Patent: May 19, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kentaro Matsunaga, Yoshihiro Yanai, Hirokazu Kato
  • Patent number: 9023222
    Abstract: According to one embodiment, a pattern forming method includes forming a first guide layer on a processed film, phase-separating a first self-assembly material with the use of the first guide layer to form a first self-assembly pattern including a first polymer portion and a second polymer portion, selectively removing the first polymer portion, forming a second guide layer with the use of the second polymer portion, and phase-separating a second self-assembly material with the use of the second guide layer to form a second self-assembly pattern including a third polymer portion and a fourth polymer portion.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: May 5, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ayako Kawanishi, Shinichi Ito, Hirokazu Kato, Shimon Maeda, Hideki Kanai
  • Patent number: 8999853
    Abstract: A pattern formation method comprises a process of forming a resist pattern with an opening that exposes a first region of a glass film arranged on a substrate through a base film; a process of forming a neutralization film above the glass film; a process of forming a directed self-assembly material layer containing a first segment and a second segment above the glass film; a process of microphase separating the directed self-assembly material layer to form a directed self-assembly pattern containing a first part that includes the first segment and a second part that includes the second segment; and a process of removing either the first part or the second part and using the other as a mask to process the base film.
    Type: Grant
    Filed: March 4, 2013
    Date of Patent: April 7, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hirokazu Kato, Ayako Kawanishi
  • Patent number: 9000497
    Abstract: A trench MOSFET is disclosed that includes a semiconductor substrate having a vertically oriented trench containing a gate. The trench MOSFET further includes a source, a drain, and a conductive element. The conductive element, like the gate is contained in the trench, and extends between the gate and a bottom of the trench. The conductive element is electrically isolated from the source, the gate, and the drain. When employed in a device such as a DC-DC converter, the trench MOSFET may reduce power losses and electrical and electromagnetic noise.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: April 7, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Tetsuo Sato, Tomoaki Uno, Hirokazu Kato, Nobuyoshi Matsuura
  • Publication number: 20150069594
    Abstract: A semiconductor device is inhibited from being degraded in reliability. The semiconductor device has a tab including a top surface, a bottom surface, and a plurality of side surfaces. Each of the side surfaces of the tab has a first portion continued to the bottom surface of the tab, a second portion located outwardly of the first portion and continued to the top surface of the tab, and a third portion located outwardly of the second portion and continued to the top surface of the tab to face the same direction as each of the first and second portions. In planar view, the outer edge of the semiconductor chip is located between the third portion and the second portion of the tab, and the outer edge of an adhesive material fixing the semiconductor chip to the tab is located between the semiconductor chip and the second portion.
    Type: Application
    Filed: November 12, 2014
    Publication date: March 12, 2015
    Inventors: Keita TAKADA, Tadatoshi DANNO, Hirokazu KATO
  • Publication number: 20150044874
    Abstract: According to one embodiment, a pattern formation method includes: forming a first guide layer having of first openings exposing a surface of an underlayer, and the first openings being arranged in a first direction; forming a second guide layer on the underlayer and on the first guide layer, the second guide layer extending in the first direction, the second guide layer dividing each of the first openings into the first opening portion and the second opening portion, and the second guide layer being sandwiched by a first opening portion and a second opening portion; forming a block copolymer layer in each of the first opening portion and the second opening portion; forming a first layer and a second layer surrounded by the first layer in each of the first opening portion and the second opening portion by phase-separating the block copolymer layer; and removing the second layer.
    Type: Application
    Filed: February 12, 2014
    Publication date: February 12, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kentaro MATSUNAGA, Yoshihiro YANAI, Hirokazu KATO