Abstract: A light emitting element of one or more embodiments includes a first electrode, a second electrode oppositely to the first electrode, and an emission layer between the first electrode and the second electrode. The light emitting element of one or more embodiments includes a polycyclic compound represented by a specific chemical structure in the emission layer, thereby showing improved emission efficiency and life characteristics.

Abstract: [Object] To improve analysis precision of communication characteristic, while minimizing the calculation amount, to determine a local dead area, thereby providing useful information for cell site design. [Solving Means] There are included the steps of: determining, on the basis of the maximum population of an area to be analyzed, an area attribute of big city, local city or rural area (S2); accepting the designation of a target building out of buildings in the area to be analyzed; finding that one or those ones of analyzing methods including quota analysis, topology analysis and geographic feature analysis which are associated with the determined area attribute, and executing a local analysis of the communication characteristic of the target building (S3-S5); and correcting, on the basis of the analysis result, the referential estimated value (A-value) of the area to be analyzed, and outputting the corrected value as a communication characteristic value of the target building (S6).

Abstract: [Object] To improve analysis precision of communication characteristic, while minimizing the calculation amount, to determine a local dead area, thereby providing useful information for cell site design. [Solving Means] There are included the steps of: determining, on the basis of the maximum population of an area to be analyzed, an area attribute of big city, local city or rural area (S2); accepting the designation of a target building out of buildings in the area to be analyzed; finding that one or those ones of analyzing methods including quota analysis, topology analysis and geographic feature analysis which are associated with the determined area attribute, and executing a local analysis of the communication characteristic of the target building (S3-S5); and correcting, on the basis of the analysis result, the referential estimated value (A-value) of the area to be analyzed, and outputting the corrected value as a communication characteristic value of the target building (S6).

Abstract: A system includes a calculation master storage unit to store a calculation master that is required for estimating the number of visitors to steady mobility facilities within a predetermined period of time, and is obtained by further classifying the steady mobility facilities by type, and a calculation master that is required for estimating the number of visitors to variable mobility facilities within a predetermined period of time, and is based on an actual survey value for each type obtained by further classifying the variable mobility facilities by type, and a building visitor number calculation unit to extract a name of a facility from map information, estimate a type of the facility based on the name, and refer to the calculation master corresponding to the type from the calculation master storage unit based on the estimated type, to calculate an estimate value of the number of visitors to the facility.

Abstract: In a memory cell array which is constituted with flash memory, a pair of a positive memory cell and a negative memory cell, to which data with mutually opposite values are written, is plurally provided. Bit lines and I/O lines connected to the memory cells of a data reading object are charged, and then a potential WL of a word line connected to the data reading object memory cells is raised. Hence, currents flow in the data reading object memory cells in accordance with the data that were written, and consequently one of a potential BL and a potential BLN of the I/O lines begins to fall. When one of the potentials BL and BLN falls below the circuit threshold of a sense amplifier, reading data is established, and the established reading data is outputted as a sense amplifier output signal SAOUT.

Abstract: In a memory cell array which is constituted with flash memory, a pair of a positive memory cell and a negative memory cell, to which data with mutually opposite values are written, is plurally provided. Bit lines and I/O lines connected to the memory cells of a data reading object are charged, and then a potential WL of a word line connected to the data reading object memory cells is raised. Hence, currents flow in the data reading object memory cells in accordance with the data that were written, and consequently one of a potential BL and a potential BLN of the I/O lines begins to fall. When one of the potentials BL and BLN falls below the circuit threshold of a sense amplifier, reading data is established, and the established reading data is outputted as a sense amplifier output signal SAOUT.

Abstract: In a step-up booster circuit, a number of pump circuits are connected in series. Pump control signals are outputted from a pump control circuit, and the pump circuits accordingly generate a required raised voltage by stepping up voltages of signals inputted to the respective pump circuits. The step-up circuit includes an activation control circuit which generates a pump activation signal in accordance with provided signals, which direct operation of the step-up circuit. The pump control circuit controls output of the pump control signals in accordance with a voltage of the pump activation signal.

Abstract: In a memory cell array which is constituted with flash memory, a pair of a positive memory cell and a negative memory cell, to which data with mutually opposite values are written, is plurally provided. Bit lines and I/O lines connected to the memory cells of a data reading object are charged, and then a potential WL of a word line connected to the data reading object memory cells is raised. Hence, currents flow in the data reading object memory cells in accordance with the data that were written, and consequently one of a potential BL and a potential BLN of the I/O lines begins to fall. When one of the potentials BL and BLN falls below the circuit threshold of a sense amplifier, reading data is established, and the established reading data is outputted as a sense amplifier output signal SAOUT.

Abstract: In a step-up booster circuit, a number of pump circuits are connected in series. Pump control signals CLKA and CLKB are outputted from a pump control circuit, and the pump circuits accordingly generate a required raised voltage VWL by stepping up voltages of signals inputted to the respective pump circuits. The step-up circuit includes an activation control circuit which generates a pump activation signal PMPENN in accordance with signals SAEND and MPMPENN, which direct operation of the step-up circuit. The pump control circuit controls output of the pump control signals CLKA and CLKB in accordance with a voltage of the pump activation signal PMPENN.

Abstract: In a memory cell array which is constituted with flash memory, a pair of a positive memory cell and a negative memory cell, to which data with mutually opposite values are written, is plurally provided. Bit lines and I/O lines connected to the memory cells of a data reading object are charged, and then a potential WL of a word line connected to the data reading object memory cells is raised. Hence, currents flow in the data reading object memory cells in accordance with the data that were written, and consequently one of a potential BL and a potential BLN of the I/O lines begins to fall. When one of the potentials BL and BLN falls below the circuit threshold of a sense amplifier, reading data is established, and the established reading data is outputted as a sense amplifier output signal SAOUT.

Abstract: A nonvolatile memory device includes a memory cell array, a control circuit, a voltage boost circuit, a timer circuit, a discharge circuit and a sensor circuit. The control circuit generates an erase execution (EE) signal in response to an erase command (EC) signal, stops the EE signal and generates a discharge control (DC) signal in response to an erase termination (ET) signal, stops the DC signal in response to a discharge termination (DT) signal, and stops the EE signal and the DC signal in response to a reset signal. The boost circuit provides high voltage in response to the EE signal. The timer circuit generates the ET signal after receiving the EE signal. The discharge circuit discharges the high voltage and the sensor is enabled in response to the DC signal or the reset signal. The sensor generates the DT signal when the high voltage drops to a predetermined voltage.

Abstract: An insulating sheet which connects a semiconductor chip and a wiring substrate is provided between the semiconductor chip and the wiring substrate. The insulating sheet has windows therethrough at positions corresponding to those of connection pads of the wiring substrate and has leads, one end of each of the leads being fixed on the sheet and the other end of each of the leads protruding from the opposite surface of the sheet through a window. Each of solder balls of the semiconductor chip is connected to the fixed one end of one of the leads, and each of the connection pads is connected to the other end of each of the leads to electrically connect the semiconductor chip and the wiring substrate.

Abstract: A nonvolatile memory device includes a memory cell array, a control circuit, a voltage boost circuit, a timer circuit, a discharge circuit and a sensor circuit. The control circuit generates an erase execution (EE) signal in response to an erase command (EC) signal, stops the EE signal and generates a discharge control (DC) signal in response to an erase termination (ET) signal, stops the DC signal in response to a discharge termination (DT) signal, and stops the EE signal and the DC signal in response to a reset signal. The boost circuit provides high voltage in response to the EE signal. The timer circuit generates the ET signal after receiving the EE signal. The discharge circuit discharges the high voltage and the sensor is enabled in response to the DC signal or the reset signal. The sensor generates the DT signal when the high voltage drops to a predetermined voltage.

Abstract: An insulating sheet which connects a semiconductor chip and a wiring substrate is provided between the semiconductor chip and the wiring substrate. The insulating sheet has windows therethrough at positions corresponding to those of connection pads of the wiring substrate and has leads, one end of each of the leads being fixed on the sheet and the other end of each of the leads protruding from the opposite surface of the sheet through a window. Each of solder balls of the semiconductor chip is connected to the fixed one end of one of the leads, and each of the connection pads is connected to the other end of each of the leads to electrically connect the semiconductor chip and the wiring substrate.

Abstract: An insulating sheet which connects a semiconductor chip and a wiring substrate is provided between the semiconductor chip and the wiring substrate. The insulating sheet has windows therethrough at positions corresponding to those of connection pads of the wiring substrate and has leads, one end of each of the leads being fixed on the sheet and the other end of each of the leads protruding from the opposite surface of the sheet through a window. Each of solder balls of the semiconductor chip is connected to the fixed one end of one of the leads, and each of the connection pads is connected to the other end of each of the leads to electrically connect the semiconductor chip and the wiring substrate.

Abstract: A novel measurement method is provided capable of measuring characteristics of semiconductor integrated circuit devices without incurring the influence of external measuring means. A prescribed delay time applied to an address supplied from a microprocessor 11 to a memory 12 during normal operation is increased and a critical time where data corresponding to the address can no longer be read in by the microprocessor 11 from the memory 12 via the latch circuit 14 correctly is obtained. The delay time with which the address is supplied to the latch circuit 14 is increased with the address being supplied in a short-circuited manner to the latch circuit 14 rather than being supplied to the memory 12 and a short-circuit critical delay time where the address can no longer be read in correctly is obtained. A time difference corresponding to a difference in critical delay times is then obtained as the memory access time of the semiconductor integrated circuit device 10.

Abstract: A novel measurement method is provided capable of measuring characteristics of semiconductor integrated circuit devices without incurring the influence of external measuring means. A prescribed delay time applied to an address supplied from a microprocessor 11 to a memory 12 during normal operation is increased and a critical time where data corresponding to the address can no longer be read in by the microprocessor 11 from the memory 12 via the latch circuit 14 correctly is obtained. The delay time with which the address is supplied to the latch circuit 14 is increased with the address being supplied in a short-circuited manner to the latch circuit 14 rather than being supplied to the memory 12 and a short-circuit critical delay time where the address can no longer be read in correctly is obtained. A time difference corresponding to a difference in critical delay times is then obtained as the memory access time of the semiconductor integrated circuit device 10.

Abstract: The present invention provides a semiconductor memory capable of achieving redundancy relief for column line failure in a stable manner while realizing greater capacity and higher integration. A column decoder circuit CD11 provided in the semiconductor memory is provided with fuse blocks FB(0)˜FB(127), first decoders DA(0)˜DA(127), redundancy control circuits RL(0)˜RL(127) and RLr, second decoders DB(0)˜DB(255), DBr(0) and DBr(1) and column line drivers DV11(0)˜DV11(255), DV11r(0) and DV11r(1). A redundancy control circuit RL(k) is connected with a column line driver DV11(2k) that drives a column line CL(2k) and a column line driver DV11(2k+1) that drives a column line CL(2k+1) via second decoders DB(2k) and DB2(2k+1) respectively.

Abstract: An LSI package structure having a smaller size in which the wiring length is shortened. The wiring structure for connecting the LSI 2 with the wiring board 1 comprises first connecting terminals 3 arrayed on the LSI 2 and second connecting terminals 6 arrayed on the wiring board 1. The first connecting terminals 3 are arrayed on the outer periphery 5 of the facing surface 4 which faces the wiring board 1 and the second connecting terminals 6 are arrayed on the interfacing surface 7 which intersects with the outer periphery 5. In such a structure, the wiring board 1 is similar to the LSI 2 in size. The facing surface 4 actually intersects with the intersecting face 7 for forming a intersecting line 8. The facing surface 4 substantially intersects with the intersecting face 7 along the intersecting line 8. Such a structure makes the size of the wiring board 1 smaller than that of the LSI 2.

Abstract: A mounting assembly of an integrated circuit device includes an integrated circuit device having pads on its lower side, through holes formed in a mounting substrate at positions opposed to the pads of the integrated circuit device, and solders for connecting the pads of the integrated circuit device with the through holes. An electrode is provided on the inside wall of each through hole, and the mounting substrate includes therein wirings connected to the electrodes. The solder is filled into the through holes to such an extent that the solder filled in the through holes can be visually checked from the lower side of the substrate.