Abstract: An asynchronous semiconductor memory device includes an output circuit, which outputs data read from a memory unit, and a high impedance control circuit. The high impedance circuit is connected to the output circuit, stores a burst completion address, and compares a present address with the burst completion address. The high impedance control circuit causes a data output terminal of the output circuit to enter a high impedance state when the present address substantially coincides with the burst completion address. Due to the high impedance control circuit, an exclusive terminal for high impedance control is not necessary.

Abstract: A semiconductor memory device having serial access read mode including a latency period and a serial access period is provided. Semiconductor memory device (100) can include sense amplifier (110), a reference voltage generator (200), and a period detection circuit (101). Period detection circuit (101) can provide a control signal (RCL) indicating the latency period or the serial access period. Reference voltage generator (200) can provide a reference voltage (REF) having a first potential during the latency period and a second potential during the serial access period. In this manner, it may be possible to increase the speed of reading memory cell data by reducing the timing differences between reading a memory cell having a first data state and a memory cell having a second data state.

Abstract: A semiconductor memory with NAND type memory cells includes word drive circuits and selecting circuits. The word drive circuits receive first row selection signals for selecting memory cell blocks connected in series and second row selection signals for selecting given memory cells in the memory cell blocks. The selecting circuits receive the first row selection signals and control gates of memory cell block selection transistors connected in series with the memory cell blocks. Each of the word drive circuits includes a switching speed delaying circuit which causes a switching speed of selecting the memory cell blocks through the first row selection signals to be slower than a switching speed of selecting the given memory cells through the second row selection signals. The switching speed delaying circuit may be realized by inserting a resistor in a drain of each of the memory cell block selection transistors in the NOR gates.

Abstract: In order to decrease peak value of current consumed by sense amplifiers provided in a high-speed read-out semiconductor memory for sensing and amplifying data of certain words of addresses having the same upper bits with upper bits of a read-out address when the upper bits are changed from those of its preceding read-out address, the sense amplifiers are divided into some groups. A group of sense amplifiers for sensing and amplifying data of words including a word indicated by the read-out address is activated firstly and other groups are controlled to be activated a little delayed according to logic of lower bits of the read-out address when the upper bits are changed. Therefore, the peak value of the current consumption Can be decreased without any operational delay.

Abstract: A semiconductor memory device, in which in each unit circuit of a data output circuit, a resistor is connected to an input terminal of an inverter for performing a buffering amplification, and a transfer gate is turned on (closed) to short-circuit both ends of the resistor so as to pass corrected data output from an error correction circuit not via the resistor but directly to the inverter when a bit corresponding to an error check signal output from an error check circuit has an active level, resulting in a reduced time for outputting the corrected data.