Patents by Inventor Hirokazu So

Hirokazu So has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190391762
    Abstract: A memory controller includes an address converter configured to convert an address designated by a host device for writing and reading into a physical address of a non-volatile memory, and an invalid-area manager configured to manage an invalid area of the non-volatile memory, the address converter making no reference to the invalid area, and, upon receipt of an invalid-data read command from the host device, data in the invalid area, managed by the invalid-area manager, of the non-volatile memory is output to the host device.
    Type: Application
    Filed: June 14, 2019
    Publication date: December 26, 2019
    Inventors: Shigekazu KOGITA, Toshiyuki HONDA, Hirokazu SO, Masato SUTO
  • Patent number: 10324664
    Abstract: A memory controller includes: a memory that holds a physical block counter including the number of erase times, a logical block counter including the number of write times, and a logical-physical conversion table; and a control unit that writes data to any physical block address. When the control unit receives a writing data instruction, the control unit updates the number of write times corresponding to the write destination logical block address, if the number of write times corresponding to the write destination logical block address is large, the control unit allocates to the write destination logical block address a physical block address with the number of erase times which is small among spare blocks not allocated to the logical block addresses in the logical-physical conversion table, updates the number of erase times corresponding to the allocated physical block address, and updates the logical-physical conversion table.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: June 18, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Hirokazu So, Toshiyuki Honda, Shigekazu Kogita
  • Patent number: 9965202
    Abstract: A non-volatile storage device of the present disclosure includes non-volatile memory configured to have a plurality of areas for storing data, and a memory controller configured to write the data to the non-volatile memory and to read the data from the non-volatile memory. The memory controller includes a memory interface (I/F) connected to the non-volatile memory, a threshold calculator calculating a threshold for the number of error bits of the data based on a storage condition in the case of storing the data in the non-volatile memory without power, and a refresh controller determining whether refresh processing of the data is necessary, based on the threshold and the number of error bits of the data, and executing the refresh processing of the data if the refresh processing of the data is necessary.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: May 8, 2018
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Shigekazu Kogita, Hirokazu So, Toshiyuki Honda
  • Patent number: 9778857
    Abstract: A recording device operates in accordance with an instruction from an access device. The recording device comprising a nonvolatile memory that stores data, a communication unit that receives an instruction issued by the access device, and a memory controller that controls the nonvolatile memory. When a recording instruction for recording data into the nonvolatile memory is received from the access device, the memory controller starts recording of data into the nonvolatile memory. When the memory controller receives from the access device a suspension instruction for suspending the recording of data, the memory controller stores suspension information into the nonvolatile memory, the suspension information indicating a suspended position as a position in a recording area of the nonvolatile memory at which the data is being recorded upon reception of the suspension instruction.
    Type: Grant
    Filed: February 2, 2015
    Date of Patent: October 3, 2017
    Assignee: Panasonic Intellectual Property Management Co., Ltd
    Inventors: Takuji Maeda, Masayuki Toyama, Hirokazu So
  • Publication number: 20170269870
    Abstract: A memory controller controls a nonvolatile memory having physical blocks. The memory controller includes a control unit and a host interface unit. The control unit writes data into a physical block. The host interface unit receives and transmits data from and to the external device. The control unit manages first vacant blocks and second vacant blocks based on a physical-block management table for managing states of the physical blocks. The first vacant block can be used in garbage collection processing of arranging data stored in the nonvolatile memory. The second vacant block cannot be used in garbage collection processing. The control unit increases a quantity of the second vacant blocks when the control unit does not receive an instruction from the external device. The control unit writes data into the second vacant blocks when the control unit receives an instruction for writing data from the external device.
    Type: Application
    Filed: November 21, 2016
    Publication date: September 21, 2017
    Inventors: Hirokazu SO, Toshiyuki HONDA
  • Publication number: 20160283163
    Abstract: A memory controller includes: a memory that holds a physical block counter including the number of erase times, a logical block counter including the number of write times, and a logical-physical conversion table; and a control unit that writes data to any physical block address. When the control unit receives a writing data instruction, the control unit updates the number of write times corresponding to the write destination logical block address, if the number of write times corresponding to the write destination logical block address is large, the control unit allocates to the write destination logical block address a physical block address with the number of erase times which is small among spare blocks not allocated to the logical block addresses in the logical-physical conversion table, updates the number of erase times corresponding to the allocated physical block address, and updates the logical-physical conversion table.
    Type: Application
    Filed: March 24, 2016
    Publication date: September 29, 2016
    Inventors: Hirokazu SO, Toshiyuki HONDA, Shigekazu KOGITA
  • Publication number: 20160283150
    Abstract: A non-volatile storage device of the present disclosure includes non-volatile memory configured to have a plurality of areas for storing data, and a memory controller configured to write the data to the non-volatile memory and to read the data from the non-volatile memory. The memory controller includes a memory interface (I/F) connected to the non-volatile memory, a threshold calculator calculating a threshold for the number of error bits of the data based on a storage condition in the case of storing the data in the non-volatile memory without power, and a refresh controller determining whether refresh processing of the data is necessary, based on the threshold and the number of error bits of the data, and executing the refresh processing of the data if the refresh processing of the data is necessary.
    Type: Application
    Filed: March 24, 2016
    Publication date: September 29, 2016
    Inventors: Shigekazu KOGITA, Hirokazu SO, Toshiyuki HONDA
  • Publication number: 20150149690
    Abstract: A recording device operates in accordance with an instruction from an access device. The recording device comprising a nonvolatile memory that stores data, a communication unit that receives an instruction issued by the access device, and a memory controller that controls the nonvolatile memory. When a recording instruction for recording data into the nonvolatile memory is received from the access device, the memory controller starts recording of data into the nonvolatile memory. When the memory controller receives from the access device a suspension instruction for suspending the recording of data, the memory controller stores suspension information into the nonvolatile memory, the suspension information indicating a suspended position as a position in a recording area of the nonvolatile memory at which the data is being recorded upon reception of the suspension instruction.
    Type: Application
    Filed: February 2, 2015
    Publication date: May 28, 2015
    Inventors: Takuji MAEDA, Masayuki TOYAMA, Hirokazu SO
  • Patent number: 8977802
    Abstract: Provided is a method for stabilizing and increasing the speed of processing for writing a plurality of different-sized files such as a video file and a management file in parallel in the case where the area in a non-volatile memory of an information recording module is managed by a file system. An access module (1) includes a means for retaining sequential areas in logical block units as areas for writing file data, and a means for realizing file data addition and overwriting by writing data to logical blocks and changing links in a FAT regardless of whether file data addition or overwriting is performed. Writing to the information recording module is performed by writing to sequential addresses in the logical blocks. This realizes the stabilization of and an increase in the file data recording speed by suppressing needless copy processing performed in the information recording module 2 in the case of recording a plurality of files such as a video file and a management file in parallel.
    Type: Grant
    Filed: October 19, 2010
    Date of Patent: March 10, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Takuji Maeda, Masayuki Toyama, Hirokazu So, Yoshinori Nakashima, Katsumi Watanabe, Masafumi Nosaka
  • Patent number: 8898420
    Abstract: A non-volatile storage device, which communicates with an access device and carries out reading and/or writing of data in accordance with a command from the access device, the device comprises one or more non-volatile memories for storing data and a memory controller for carrying out control of the non-volatile memory. The memory controller writes data to the error correcting group and writes a provisional error correcting code with respect to the data to the parity table if a data size is smaller than the first size when writing the data.
    Type: Grant
    Filed: May 4, 2012
    Date of Patent: November 25, 2014
    Assignee: Panasonic Corporation
    Inventors: Hirokazu So, Toshiyuki Honda
  • Patent number: 8856427
    Abstract: A non-volatile storage device comprises non-volatile memories for storing data; and a memory controller for carrying out control of the non-volatile memory. The memory controller stores second error correcting code as well as first error correcting code stored in the same page of the data. The memory controller, when writing data smaller than a predefined size, does not add the second error correcting code, and stores duplexed data of the data and the first correcting code in a different page. The memory controller, when reading, corrects data using the first and/or second correcting code. The valid data management table manages which logical block stores valid data with respect to an identical logical address.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: October 7, 2014
    Assignee: Panasonic Corporation
    Inventors: Hirokazu So, Toshiyuki Honda
  • Patent number: 8688896
    Abstract: A digital still camera performs temporary high-speed writing when capturing a large number of images in a short time. Lengthy processing for erased block allocation or copying performed inside a nonvolatile storage device may disable the captured images to be written completely (may cause some frames to drop). A nonvolatile storage system includes an access device (1001) and a nonvolatile storage device (1002). A button operation of a user on the access device (1001) causes the mode of data writing to the nonvolatile storage device (1002) to be switched. Temporary high-speed writing is performed into a physical block of a nonvolatile memory (27) from which a plurality of data pieces with different logical addresses and different data sizes have been erased. After the temporary high-speed writing, the written data is relocated into a user storage area (272), and an erased block is newly allocated for subsequent temporary high-speed data writing.
    Type: Grant
    Filed: May 13, 2010
    Date of Patent: April 1, 2014
    Assignee: Panasonic Corporation
    Inventors: Masahiro Nakamura, Hirokazu So, Masahiro Nakanishi
  • Patent number: 8656110
    Abstract: When multiple pieces of content data are being recorded continuously to a nonvolatile storage device having page cache function, a preparation time before starting next content data recording is reduced. When a cache releasing section of a nonvolatile storage device (1) receives cache releasing from an access device (2), it releases addresses included in one logical block among multiple addresses which are cache objects at the same time. Further, the nonvolatile storage device (1) includes a cache information outputting section which outputs information regarding a time period required for releasing addresses which are cache objects outside, and the access device (2) refers to the information to select the address to be an object of releasing.
    Type: Grant
    Filed: August 10, 2010
    Date of Patent: February 18, 2014
    Assignee: Panasonic Corporation
    Inventors: Hirokazu So, Takuji Maeda, Masayuki Toyama
  • Patent number: 8656252
    Abstract: A non-volatile storage device includes one or more non-volatile memories for storing data, and a memory controller for carrying out the control of the non-volatile memory. The non-volatile memory includes the plurality of blocks, which are erase units, and the block includes the plurality of pages, which are write units of data, in each of the blocks at least one set of pages existing which include at least two pages sharing one word line. The memory controller configures a plurality of error correcting groups, each including at least one data page, which is a page for storing data, and at least one error correcting code page for storing a code for error correcting calculation of the data page, and assigns a page of a separate word line with respect to each of the data page and the error correcting page in the same error correcting group.
    Type: Grant
    Filed: May 3, 2012
    Date of Patent: February 18, 2014
    Assignee: Panasonic Corporation
    Inventors: Hirokazu So, Toshiyuki Honda
  • Publication number: 20140040631
    Abstract: A memory device includes a memory configured to store a secret key, an interface configured to communicate with an the external apparatus in a first communication method and a second communication method that is faster than the first communication method, and a controller configured to control the memory and the interface. The controller is configured to decrypt an encrypted management data encryption key, an encrypted management data, an encrypted individual data encryption key and an encrypted individual data according to communication method, record the decrypted individual data in the memory, decrypt an encrypted application key and an encrypted application according to communication method, and record the decrypted application in the memory.
    Type: Application
    Filed: August 14, 2013
    Publication date: February 6, 2014
    Inventors: Hirokazu SO, Yasuo TAKEUCHI, Yoshihiko TAKAGI, Osamu SASAKI
  • Patent number: 8554987
    Abstract: The nonvolatile memory device prevents data writing from temporarily slowing down significantly in the middle of writing data to a block when an access device writes all the data in the block in units of a smaller size than the block. The nonvolatile memory device comprises a memory controller including an interface unit configured to receive a first command that identifies a first write range for writing data, and a second command that identifies a second write range that is a part of the first write range and orders to write data to the second write range, an address management unit configured to determine, before data is written into a nonvolatile memory, a new block for writing data to the first write range based on the first command, and a read/write control unit configured to write data to the new block in response to the second command.
    Type: Grant
    Filed: May 14, 2010
    Date of Patent: October 8, 2013
    Assignee: Panasonic Corporation
    Inventors: Hirokazu So, Masayuki Toyama
  • Patent number: 8549213
    Abstract: A nonvolatile storage device includes a nonvolatile memory that stores data and a memory controller that controls the nonvolatile memory. The memory controller accepts a pause instruction to pause writing from the access device within a period in which data from the access device are written, and writes the data received from the access device to the nonvolatile memory within a predetermined time interval, then pauses the writing and accepts read and/or write of new data from the access device.
    Type: Grant
    Filed: February 8, 2011
    Date of Patent: October 1, 2013
    Assignee: Panasonic Corporation
    Inventors: Hirokazu So, Toshiyuki Honda
  • Patent number: 8397303
    Abstract: In a memory controller according to the present invention, an external I/F unit receives ID information associated with data from the outside of a non-volatile memory, and a recording controller manages a recording position of the data in the non-volatile memory based on the ID information, so that an amount of time necessary for the retrieval of rights information based on the ID information is reduced.
    Type: Grant
    Filed: February 10, 2009
    Date of Patent: March 12, 2013
    Assignee: Panasonic Corporation
    Inventors: Makoto Ochi, Hiroki Etoh, Masahiro Nakanishi, Hirokazu So, Hiroshi Sakurai, Masato Suto
  • Patent number: 8393005
    Abstract: A recording medium (100) for storing content that can be read and written by a host device stores a content key (a key that is used for encrypting content) (805a) encrypted in a first format, and a content key (805b) that is encrypted in a second format for content that is the same as the content related to the content key (805a) encrypted in the first format. The first format is, for example, a format used for distributed content, and the second format is a format used with local content.
    Type: Grant
    Filed: June 28, 2005
    Date of Patent: March 5, 2013
    Assignee: Panasonic Corporation
    Inventors: Makoto Ochi, Hirokazu So, Shinji Inoue, Kazuya Fujimura, Takuji Maeda, Masato Suto, Yukiko Inoue
  • Publication number: 20120317341
    Abstract: A non-volatile storage device, which communicates with an access device and carries out reading and/or writing of data in accordance with a command from the access device, the device comprises one or more non-volatile memories for storing data and a memory controller for carrying out control of the non-volatile memory. The memory controller writes data to the error correcting group and writes a provisional error correcting code with respect to the data to the parity table if a data size is smaller than the first size when writing the data.
    Type: Application
    Filed: May 4, 2012
    Publication date: December 13, 2012
    Inventors: Hirokazu So, Toshiyuki Honda