Patents by Inventor Hiroki Fujisawa

Hiroki Fujisawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Latency counter, semiconductor memory device including the same, and data processing system
    Patent number: 8208340
    Abstract: A latency counter includes an input selecting circuit that selects one of a plurality of signal paths and supplies an internal command to the selected signal path, a shift circuit that switches a correspondence relation between the signal paths and a latch circuit, and an output selecting circuit that causes the internal command taken in the latch circuit to be output. The input selection circuit includes a timing control circuit allocated to each of the signal paths. The timing control circuit includes an SR latch circuit that is set by the internal command and is reset in response to deactivation of a corresponding count value. Therefore, it becomes possible to suppress shortening of an active period of the internal command that is output from the input selecting circuit.
    Type: Grant
    Filed: September 7, 2010
    Date of Patent: June 26, 2012
    Assignee: Elpida Memory, Inc.
    Inventor: Hiroki Fujisawa
  • Output circuit for semiconductor device, semiconductor device having output circuit, and method of adjusting characteristics of output circuit
    Patent number: 8198911
    Abstract: To decrease the circuit scale necessary for the calibration of the output circuit and to decrease the time required for the calibration operation. The invention includes a first output buffer and a second output buffer that are connected to a data pin, and a calibration circuit that is connected to a calibration pin. The first output buffer and the second output buffer include plural unit buffers. The unit buffers have mutually the same circuit structures. With this arrangement, the impedances of the first output buffer and the second output buffer can be set in common, based on the calibration operation using the calibration circuit. Consequently, both the circuit scale necessary for the calibration operation and the time required for the calibration operation can be decreased.
    Type: Grant
    Filed: September 16, 2010
    Date of Patent: June 12, 2012
    Assignee: Elpida Memory, Inc.
    Inventor: Hiroki Fujisawa
  • SEMICONDUCTOR DEVICE HAVING SENSE AMPLIFIER
    Publication number: 20120134227
    Abstract: For example, four driver transistors are arranged in wells so as to adjoin both sides of each of two element isolation regions. Two pairs of cross-coupled sense transistors are arranged in the wells at positions farther from the element isolation regions than the driver transistors are. Such an arrangement provides more than a certain distance between the sense transistors and the respective corresponding element isolation regions. This reduces the effect of a phenomenon that threshold of a transistor varies according to a distance from an element isolation region. As a result, it is possible to exactly match the characteristics of each pair of cross-coupled transistors.
    Type: Application
    Filed: November 23, 2011
    Publication date: May 31, 2012
    Applicant: Elpida Memory, Inc.
    Inventors: Hiroki FUJISAWA, Ryuuji Takishita
  • SEMICONDUCTOR DEVICE HAVING PLURAL BANKS
    Publication number: 20120134217
    Abstract: A semiconductor device is provided with a control circuit generating a plurality of first control signals indicating timings at which column switches conduct at the time of reading and a plurality of second control signals indicating timings at which the column switches conduct at the time of writing. The control circuit activates the plurality of first control signals such that timing at which the data read from each of memory cell arrays arrives at a FIFO circuit after reception of a read instruction from outside is the same in each bank and activates the plurality of second control signals such that the column switches match a timing at which write data input from outside to a first data input/output terminal arrives at the corresponding column switch.
    Type: Application
    Filed: November 23, 2011
    Publication date: May 31, 2012
    Applicant: Elpida Memory, Inc.
    Inventors: Hiroki FUJISAWA, Yuuji Motoyama
  • Semiconductor device and method of controlling the same
    Publication number: 20120134222
    Abstract: A semiconductor device includes a data input/output circuit connected to the memory cell array via a sense circuit, and an access control circuit that controls access to the memory cell array. The access control circuit includes: a first signal unit outputting a first signal for activating or inactivating a word line; a second signal unit outputting a second signal for activating or inactivating a bit line and the sense circuit; a third signal unit outputting a third signal for starting or stopping a supply of an overdrive voltage to the sense circuit; and a fourth signal unit outputting a fourth signal for inactivating the word line. The period during which the third signal remains activated is determined in accordance with the magnitude of an external voltage. In the fourth signal unit, the timing to generate the fourth signal is determined independently of the magnitude of the external voltage.
    Type: Application
    Filed: October 24, 2011
    Publication date: May 31, 2012
    Applicant: Elpida Memory, Inc.
    Inventors: Hiroki Fujisawa, Kazuhisa Ureshino
  • SEMICONDUCTOR DEVICE HAVING PLURAL WIRING LAYERS
    Publication number: 20120126422
    Abstract: A semiconductor device includes a lower wiring layer, having signal lines and power supply lines extending in a Y-direction; an upper wiring layer having signal lines and power supply lines extending in an X-direction; via conductors provided in first overlap regions where corresponding signal lines overlap each other; and via conductors provided in second overlap regions where corresponding power supply lines overlap each other. The width in the X-direction of the first regions is wider than the widths in the X-direction of the second regions. Therefore, in the first regions, a plurality of via conductors can be provided. Moreover, the power supply lines are divided in the Y-direction to avoid interference with the first regions. On a plurality of lower-layer lines, two vias are placed at a minimum pitch containing one via.
    Type: Application
    Filed: November 17, 2011
    Publication date: May 24, 2012
    Applicant: Elpida Memory, Inc.
    Inventors: Kiyotaka Endo, Kazuteru Ishizuka, Hiroki Fujisawa
  • Semiconductor device having pull-up circuit and pull-down circuit
    Publication number: 20120119578
    Abstract: To reduce power supply noises occurring in a control circuit unit for controlling an output buffer. A semiconductor device includes unit buffers for driving a data output terminal, impedance control circuits for controlling the unit buffers, and a control circuit unit for controlling the impedance control circuits. The impedance control circuits and the control circuit unit operate by mutually-different power supplies, the control circuit unit supplies pull-up data and pull-down data in mutually reverse phase to the impedance control circuits, and the impedance control circuits convert the pull-up data and the pull-down data from reverse phase to in-phase and supply the same to the unit buffers. Thereby, a noise is difficult to occur in a power supply VDD used for the control circuit unit.
    Type: Application
    Filed: October 26, 2011
    Publication date: May 17, 2012
    Applicant: Elpida Memory, Inc.
    Inventors: Shunji Kuwahara, Hiroki Fujisawa
  • Semiconductor device having point-shift type FIFO circuit
    Publication number: 20120120753
    Abstract: For example, a semiconductor device includes latch circuits, whose input nodes are connected to an input selection circuit and whose output nodes are connected to an output selection circuit; and a control circuit, which controls the input selection circuit and the output selection circuit. The control circuit includes a shift register to generate an input pointer signal and a binary counter to generate an output pointer signal. The input selection circuit selects one of the latch circuits on the basis of a value of the input pointer signal. The output selection circuit selects one of the latch circuits on the basis of a value of the output pointer signal. Therefore, it is possible to prevent a hazard from occurring in the input selection circuit, as well as to reduce the number of signal lines that transmit the output pointer signal.
    Type: Application
    Filed: October 24, 2011
    Publication date: May 17, 2012
    Applicant: Elpida Memory, Inc.
    Inventors: Hiroki Fujisawa, Yuuji Motoyama
  • Semiconductor device including latency counter
    Publication number: 20120120754
    Abstract: For example, a semiconductor device includes a first latency counter, which selects whether to give an odd-cycle latency to an internal command signal; and a second latency counter, which gives a latency to an internal command signal at intervals of two cycles. The latency counters are connected in series. Since the number of bits in control information, which is used to set a latency, is smaller than the types of settable latency as a result, it is possible to reduce wiring density.
    Type: Application
    Filed: October 24, 2011
    Publication date: May 17, 2012
    Applicant: Elpida Memory, Inc.
    Inventor: Hiroki Fujisawa
  • SEMICONDUCTOR MEMORY DEVICE PERFORMING PARALLEL TEST OPERATION
    Publication number: 20120124436
    Abstract: A semiconductor memory device includes: first test circuits each of which operates in a first test mode in which the first test circuit receives a plurality of comparison result signals each indicating a comparison result of storage contents of a plurality of memory cells included in a memory cell array in parallel and generates a first output signal by converting the comparison result signals into serial signals or a second test mode in which the first test circuit generates a second output signal by compressing the data amount of the plurality of comparison result signals. Each of the first test circuits outputs the first and second output signals to a common bus.
    Type: Application
    Filed: November 4, 2011
    Publication date: May 17, 2012
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Tetsuaki OKAHIRO, Hiroki FUJISAWA
  • SEMICONDUCTOR DEVICE HAVING BIT LINES AND LOCAL I/O LINES
    Publication number: 20120120705
    Abstract: The present invention efficiently decides line failure and contact failure in a semiconductor device. The semiconductor device has a plurality of bit line groups in which connection with local I/O lines is controlled by the same column selection signal line. A failure detecting circuit compares a first data group read from a first bit line group and a second data group read from a second bit line group to detect whether or not connection failure (contact failure) with the column selection signal line occurs in one of the first and second bit line groups.
    Type: Application
    Filed: September 27, 2011
    Publication date: May 17, 2012
    Applicant: Elpida Memory, Inc.
    Inventors: Shingo MITSUBORI, Hiroki FUJISAWA
  • SEMICONDUCTOR CHIP AND SEMICONDUCTOR DEVICE INCLUDING THE SAME
    Publication number: 20120112540
    Abstract: A semiconductor chip includes: a data output buffer that outputs a data signal; a first power-supply pad that supplies a first power-supply potential to the data output buffer; a power-supply wiring that is connected to the first power-supply pad; a strobe output buffer that outputs a strobe signal; and a second power-supply pad that supplies a second power-supply potential to the strobe output buffer. The power-supply wiring and the second power-supply pad are electrically independent of each other. Therefore, the power-supply noise associated with the switching of the data output buffer does not spread to the strobe output buffer. Thus, it is possible to improve the quality of the strobe signal.
    Type: Application
    Filed: October 21, 2011
    Publication date: May 10, 2012
    Inventors: Hiromasa TAKEDA, Hiroki Fujisawa
  • Semiconductor device and semiconductor package including the same
    Patent number: 8144524
    Abstract: To include a plurality of pad groups each including a first data I/O pad, a first power supply pad, a second data I/O pad, and a second power supply pad arranged in order in an X direction. The first data I/O pad is connected to a first data I/O buffer, and the second data I/O pad is connected to a second data I/O buffer. The first power supply pad supplies a first power supply potential to the first and second data I/O buffers, and the second power supply pad supplies a second power supply potential to the first and second data I/O buffers. The first data I/O pad included in each of the pad groups is adjacent to the second power supply pad included in other pad group or any one of a plurality of power supply pads not included in any one of the pad groups.
    Type: Grant
    Filed: September 10, 2010
    Date of Patent: March 27, 2012
    Assignee: Elpida Memory, Inc.
    Inventors: Yoshio Mizukane, Hiroki Fujisawa
  • COUNTER CIRCUIT, LATENCY COUNTER, SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME, AND DATA PROCESSING SYSTEM
    Publication number: 20120008437
    Abstract: To provide a counter circuit capable of accurately counting a high-frequency signal in which hazard or the like is easily generated. There are provided: a frequency dividing circuit that generates first and second frequency dividing clocks, which differ in phase to each other, based on a clock signal; a first counter that counts the first frequency dividing clock; a second counter that synchronizes with the second frequency dividing clock to fetch a count value of the first counter; and a selection circuit that exclusively selects count values of the first and second counters. According to the present invention, a relation of the count values between the first and second counters is kept always constant, and thus, even when hazard occurs, the count values are only made to jump and the count values do not fluctuate.
    Type: Application
    Filed: September 16, 2011
    Publication date: January 12, 2012
    Applicant: ELPIDA MEMORY, INC.
    Inventor: Hiroki FUJISAWA
  • Output circuit of semiconductor device
    Patent number: 8085061
    Abstract: An output circuit of a semiconductor includes unit buffers, each unit buffer having transistors and resistors connected between a power source terminal VDDQ and an output terminal DQ, and transistors and resistors connected between a power source terminal VSSQ and an output terminal DQ. On-resistance values of transistors included in the unit buffers are mutually substantially the same, and resistance values of resistors included in the unit buffers are mutually different. A deviation of impedances attributable to a power source resistance can be offset based on a difference between resistance values of the resistors.
    Type: Grant
    Filed: August 27, 2007
    Date of Patent: December 27, 2011
    Assignee: Elpida Memory, Inc.
    Inventors: Hiroto Kinoshita, Hiroki Fujisawa
  • DEVICE
    Publication number: 20110279157
    Abstract: A device in which a clock generation circuit is connected to a counter circuit for controlling operation timing of a DLL circuit or the like, and the counter circuit is intermittently operated by intermittently supplying a clock signal to the counter circuit from the clock generation circuit.
    Type: Application
    Filed: July 15, 2011
    Publication date: November 17, 2011
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Yoshio MIZUKANE, Hiroki FUJISAWA
  • Counter circuit, latency counter, semiconductor memory device including the same, and data processing system
    Patent number: 8040752
    Abstract: To provide a counter circuit capable of accurately counting a high-frequency signal in which hazard or the like is easily generated. There are provided: a frequency dividing circuit that generates first and second frequency dividing clocks, which differ in phase to each other, based on a clock signal; a first counter that counts the first frequency dividing clock; a second counter that synchronizes with the second frequency dividing clock to fetch a count value of the first counter; and a selection circuit that exclusively selects count values of the first and second counters. According to the present invention, a relation of the count values between the first and second counters is kept always constant, and thus, even when hazard occurs, the count values are only made to jump and the count values do not fluctuate.
    Type: Grant
    Filed: May 18, 2009
    Date of Patent: October 18, 2011
    Assignee: Elpida Memory, Inc.
    Inventor: Hiroki Fujisawa
  • Calibration circuit, semiconductor device including the same, and data processing system
    Publication number: 20110248742
    Abstract: A method includes issuing a calibration command and performing a calibration operation in response to the calibration command. The calibration operation includes adjusting an impedance of a first replica buffer with updating a first code, the first replica buffer being substantially identical in circuit configuration to one of pull-up and pull-down circuits included in an output buffer, adjusting impedance of a second replica buffer with updating a second code, the second replica buffer being substantially identical in circuit configuration to the other of the pull-up and pull-down circuits included in the output buffer, controlling a first latch circuit to hold the first code when the impedance of the first replica buffer reaches a first level, and controlling a second latch circuit to hold the second code when the impedance of the second replica buffer reaches a second level.
    Type: Application
    Filed: June 16, 2011
    Publication date: October 13, 2011
    Applicant: Elpida Memory, Inc.
    Inventors: Fumiyuki Osanai, Hiroki Fujisawa
  • Semiconductor device having boosting circuit
    Publication number: 20110221513
    Abstract: A semiconductor device includes a boosting circuit that boosts an internal power supply voltage in a boosting range according to an external power supply voltage, an external voltage-level comparison circuit that compares the external power supply voltage and a predetermined reference voltage, and a variable resistor circuit that includes a variable resistor connected to an output terminal of the boosting circuit. The variable resistor circuit controls a resistance value of the variable resistor based on a comparison result of the external voltage-level comparison circuit.
    Type: Application
    Filed: March 11, 2011
    Publication date: September 15, 2011
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Hiroki Fujisawa, Shuichi Kubouchi, Hitoshi Tanaka
  • Semiconductor device having controlled DLL start-up period
    Patent number: 8004325
    Abstract: A device in which a clock generation circuit is connected to a counter circuit for controlling operation timing of a DLL circuit or the like, and the counter circuit is intermittently operated by intermittently supplying a clock signal to the counter circuit from the clock generation circuit.
    Type: Grant
    Filed: May 20, 2009
    Date of Patent: August 23, 2011
    Assignee: Elpida Memory, Inc.
    Inventors: Yoshio Mizukane, Hiroki Fujisawa